公开(公告)号：US20110315536A1

公开(公告)日：2011-12-29

申请号：US13038389

申请日：2011-03-02

申请人： Jeng-Maw Chiou ,  Te-Hao Tsou ,  Biing-Nan Lin ,  Tzyy-Jang Tseng

发明人： Jeng-Maw Chiou ,  Te-Hao Tsou ,  Biing-Nan Lin ,  Tzyy-Jang Tseng

IPC分类号： H03K17/975

CPC分类号： G06F3/044 ,  G06F3/043 ,  G06F3/045 ,  G06F3/046 ,  G06F2203/04112 ,  G06F2203/04113

摘要： A touch panel including a substrate, a first patterned conductive layer, a second patterned conductive layer and a circuit board is provided. The substrate has a first surface, a second surface, a first bonding area and a second bonding area. The first patterned conductive layer disposed on the first surface includes first sensing series electrically insulated from each other. The second patterned conductive layer disposed on the second surface includes second sensing series electrically insulated from each other. The circuit board includes a rigid portion, a first flexible bonding portion and a second flexible bonding portion. The first flexible bonding portion and the second flexible bonding portion are electrically connected to the rigid portion. The first flexible bonding portion is electrically connected to the first sensing series in the first bonding area. The second flexible bonding portion is electrically connected to the second sensing series in the second bonding area.

摘要翻译： 提供了包括基板，第一图案化导电层，第二图案化导电层和电路板的触摸面板。 基板具有第一表面，第二表面，第一接合区域和第二接合区域。 设置在第一表面上的第一图案化导电层包括彼此电绝缘的第一感测系列。 设置在第二表面上的第二图案化导电层包括彼此电绝缘的第二感测串联。 电路板包括刚性部分，第一柔性接合部分和第二柔性接合部分。 第一柔性接合部分和第二柔性接合部分电连接到刚性部分。 第一柔性接合部分在第一接合区域中电连接到第一传感系列。 第二柔性接合部分在第二接合区域中电连接到第二传感系列。

公开(公告)号：US09510464B2

公开(公告)日：2016-11-29

申请号：US13590815

申请日：2012-08-21

申请人： Tzyy-Jang Tseng ,  Shu-Sheng Chiang ,  Tsung-Yuan Chen

发明人： Tzyy-Jang Tseng ,  Shu-Sheng Chiang ,  Tsung-Yuan Chen

IPC分类号： H05K3/46 ,  H05K3/04 ,  H05K3/10 ,  C23C18/16 ,  H05K1/02 ,  H05K3/00

CPC分类号： H05K3/465 ,  C23C18/1612 ,  C23C18/1651 ,  C23C18/1653 ,  C23C18/1689 ,  H05K1/0265 ,  H05K3/0032 ,  H05K3/0035 ,  H05K3/045 ,  H05K3/107 ,  H05K2201/0391 ,  H05K2201/09509 ,  Y10T29/49155 ,  Y10T29/49165

摘要： A manufacturing method of a circuit board is provided. A circuit substrate having a first surface and at least a first circuit is provided. A dielectric layer having a second surface and covering the first surface and the first circuit is formed on the circuit substrate. The dielectric layer is irradiated by a laser beam to form a first intaglio pattern, a second intaglio pattern and at least a blind via. A first conductive layer is formed in the first intaglio pattern, the second intaglio pattern and the blind via. A barrier layer and a second conductive layer are formed in the second intaglio pattern and the blind via. Parts of the second conductive layer, parts of the barrier layer and parts of the first conductive layer are removed until the second surface of the dielectric layer is exposed, so as to form a patterned circuit structure.

摘要翻译： 提供电路板的制造方法。 提供具有第一表面和至少第一电路的电路基板。 具有第二表面并覆盖第一表面的电介质层和第一电路形成在电路基板上。 电介质层被激光束照射以形成第一凹版图案，第二凹版图案和至少一个盲孔。 在第一凹版图案，第二凹版图案和盲孔中形成第一导电层。 在第二凹版图案和盲孔中形成阻挡层和第二导电层。 去除第二导电层的一部分，阻挡层的一部分和第一导电层的部分直到电介质层的第二表面露出，以形成图案化的电路结构。

公开(公告)号：US20160050761A1

公开(公告)日：2016-02-18

申请号：US14535301

申请日：2014-11-06

申请人： Tzyy-Jang Tseng ,  Chien-Nan Wu

发明人： Tzyy-Jang Tseng ,  Chien-Nan Wu

IPC分类号： H05K3/00 ,  H05K1/02 ,  H05K3/04

CPC分类号： H05K3/0029 ,  H05K1/0209 ,  H05K3/045 ,  H05K3/28 ,  H05K2201/0376 ,  H05K2201/098 ,  H05K2203/025 ,  H05K2203/072

摘要： A method of manufacturing a substrate structure is provided. An insulation substrate having an upper surface is provided. A portion of the upper surface of the insulation substrate is irradiated by a first laser beam so as to form a first intaglio pattern. The first laser beam is IR laser beam or fiber laser beam. The first intaglio pattern has a modification surface. A first metal layer is formed on the upper surface of the insulation substrate, and covers the upper surface of the insulation layer and the modification surface of the first intaglio pattern, and fills up the first intaglio pattern. A grinding process is performed on the first metal layer so as to expose the upper surface of the insulation substrate and define a first patterned circuit layer. A first upper surface of the first patterned circuit layer is aligned with the upper surface of the insulation substrate.

摘要翻译： 提供一种制造衬底结构的方法。 提供具有上表面的绝缘基板。 绝缘基板的上表面的一部分被第一激光束照射，以形成第一凹版图案。 第一激光束是IR激光束或光纤激光束。 第一个凹版图案具有修饰面。 第一金属层形成在绝缘基板的上表面上，并且覆盖绝缘层的上表面和第一凹版图案的修改表面，并填满第一凹版图案。 在第一金属层上进行研磨处理，以露出绝缘基板的上表面并限定第一图案化电路层。 第一图案化电路层的第一上表面与绝缘基板的上表面对准。

公开(公告)号：US08952268B2

公开(公告)日：2015-02-10

申请号：US13543893

申请日：2012-07-09

申请人： Dyi-Chung Hu ,  Ming-Chih Chen ,  Tzyy-Jang Tseng

发明人： Dyi-Chung Hu ,  Ming-Chih Chen ,  Tzyy-Jang Tseng

IPC分类号： H05K1/11

CPC分类号： H01L21/481 ,  C25D1/003 ,  H05K1/113 ,  H05K3/424 ,  H05K3/4647 ,  H05K3/4682 ,  H05K2201/10378 ,  H05K2203/0152 ,  H05K2203/0726 ,  H05K2203/0733 ,  Y10T29/49155 ,  Y10T156/10

摘要： A manufacturing method of an interposed substrate is provided. A photoresist layer is formed on a metal carrier. The photoresist layer has plural of openings exposing a portion of the metal carrier. Plural of metal passivation pads and plural of conductive pillars are formed in the openings. The metal passivation pads cover a portion of the metal carrier exposed by openings. The conductive pillars are respectively stacked on the metal passivation pads. The photoresist layer is removed to expose another portion of the metal carrier. An insulating material layer is formed on the metal carrier. The insulating material layer covers the another portion of the metal carrier and encapsulates the conductive pillars and the metal passivation pads. An upper surface of the insulating material layer and a top surface of each conductive pillar are coplanar. The metal carrier is removed to expose a lower surface of the insulating material layer.

摘要翻译： 提供了一种插入式基板的制造方法。 在金属载体上形成光致抗蚀剂层。 光致抗蚀剂层具有暴露金属载体的一部分的多个开口。 多个金属钝化垫和多个导电柱形成在开口中。 金属钝化垫覆盖由开口暴露的金属载体的一部分。 导电柱分别堆叠在金属钝化垫上。 去除光致抗蚀剂层以暴露金属载体的另一部分。 在金属载体上形成绝缘材料层。 绝缘材料层覆盖金属载体的另一部分并封装导电柱和金属钝化垫。 绝缘材料层的上表面和每个导电柱的顶表面是共面的。 去除金属载体以暴露绝缘材料层的下表面。

公开(公告)号：US08912642B2

公开(公告)日：2014-12-16

申请号：US13542914

申请日：2012-07-06

申请人： Tzyy-Jang Tseng ,  Chung-W. Ho

发明人： Tzyy-Jang Tseng ,  Chung-W. Ho

IPC分类号： H01L33/44 ,  H01L23/498 ,  H01L23/00

CPC分类号： H05K3/0091 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/12042 ,  H01L2924/15311 ,  H05K3/4007 ,  H05K3/4647 ,  H05K3/4682 ,  H05K3/4685 ,  Y10T29/49155 ,  H01L2924/00

摘要： A packaging substrate includes a first dielectric layer, a first circuit layer, a first metal bump, and a built-up structure. The first metal bump and the first circuit layer are embedded in and exposed from two surfaces of the first dielectric layer. The end of the first metal bump is embedded in the first circuit layer and between the first circuit layer and the first dielectric layer. In addition, a conductive seedlayer is disposed between the first circuit layer and the first metal bump. The built-up structure is disposed on the first circuit layer and the first dielectric layer. The outmost layer of the built-up structure has a plurality of conductive pads. Compared to the prior art, the present invention can effectively improve the warpage problem of the conventional packaging substrate.

摘要翻译： 封装基板包括第一介电层，第一电路层，第一金属凸块和积层结构。 第一金属凸块和第一电路层嵌入并暴露于第一电介质层的两个表面。 第一金属凸块的端部嵌入在第一电路层中，并且在第一电路层和第一电介质层之间。 此外，导电种子层设置在第一电路层和第一金属凸块之间。 所述积层结构设置在所述第一电路层和所述第一电介质层上。 积层结构的最外层具有多个导电垫。 与现有技术相比，本发明可以有效地改善传统封装基板的翘曲问题。

公开(公告)号：US08835992B2

公开(公告)日：2014-09-16

申请号：US13183816

申请日：2011-07-15

申请人： Tzyy-Jang Tseng ,  Dyi-Chung Hu

发明人： Tzyy-Jang Tseng ,  Dyi-Chung Hu

IPC分类号： H01L27/148 ,  H01L31/062 ,  H01L27/146

CPC分类号： H01L27/14632 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14629 ,  H01L27/14636

摘要： An electronic device and a method of fabricating the same are provided. The electronic device includes: a photodiode layer; a wiring layer formed on the first surface of the photodiode layer; a plurality of electrical contact pads formed on the wiring layer; a passivation layer formed on the wiring layer and the electrical contact pads; an antireflective layer formed on the second surface of the photodiode layer; a color filter layer formed on the antireflective layer; a dielectric layer formed on the antireflective layer and the color filter layer; and a microlens layer formed on the dielectric layer, allowing the color filter layer, the dielectric layer and the microlens layer to define an active region within which the electrical contact pads are positioned. As the electrical contact pads are positioned within the active region, an area of the substrate used for an inactive region can be eliminated.

摘要翻译： 提供一种电子设备及其制造方法。 该电子设备包括：光电二极管层; 形成在光电二极管层的第一表面上的布线层; 形成在所述布线层上的多个电接触焊盘; 形成在所述布线层和所述电接触焊盘上的钝化层; 形成在光电二极管层的第二表面上的抗反射层; 形成在所述抗反射层上的滤色层; 形成在抗反射层和滤色器层上的电介质层; 以及形成在电介质层上的微透镜层，允许滤色器层，电介质层和微透镜层限定其中定位电接触垫的有源区。 当电接触垫位于有源区域内时，可以消除用于非活性区域的衬底的区域。

公开(公告)号：US20130313011A1

公开(公告)日：2013-11-28

申请号：US13543893

申请日：2012-07-09

申请人： Dyi-Chung Hu ,  Ming-Chih Chen ,  Tzyy-Jang Tseng

发明人： Dyi-Chung Hu ,  Ming-Chih Chen ,  Tzyy-Jang Tseng

IPC分类号： H05K1/11 ,  C25D5/02 ,  H05K3/10 ,  H05K3/00 ,  B23K31/02

CPC分类号： H01L21/481 ,  C25D1/003 ,  H05K1/113 ,  H05K3/424 ,  H05K3/4647 ,  H05K3/4682 ,  H05K2201/10378 ,  H05K2203/0152 ,  H05K2203/0726 ,  H05K2203/0733 ,  Y10T29/49155 ,  Y10T156/10

摘要： A manufacturing method of an interposed substrate is provided. A photoresist layer is formed on a metal carrier. The photoresist layer has plural of openings exposing a portion of the metal carrier. Plural of metal passivation pads and plural of conductive pillars are formed in the openings. The metal passivation pads cover a portion of the metal carrier exposed by openings. The conductive pillars are respectively stacked on the metal passivation pads. The photoresist layer is removed to expose another portion of the metal carrier. An insulating material layer is formed on the metal carrier. The insulating material layer covers the another portion of the metal carrier and encapsulates the conductive pillars and the metal passivation pads. An upper surface of the insulating material layer and a top surface of each conductive pillar are coplanar. The metal carrier is removed to expose a lower surface of the insulating material layer.

摘要翻译： 提供了一种插入式基板的制造方法。 在金属载体上形成光致抗蚀剂层。 光致抗蚀剂层具有暴露金属载体的一部分的多个开口。 多个金属钝化垫和多个导电柱形成在开口中。 金属钝化垫覆盖由开口暴露的金属载体的一部分。 导电柱分别堆叠在金属钝化垫上。 去除光致抗蚀剂层以暴露金属载体的另一部分。 在金属载体上形成绝缘材料层。 绝缘材料层覆盖金属载体的另一部分并封装导电柱和金属钝化垫。 绝缘材料层的上表面和每个导电柱的顶表面是共面的。 去除金属载体以暴露绝缘材料层的下表面。

公开(公告)号：US08578600B2

公开(公告)日：2013-11-12

申请号：US12783837

申请日：2010-05-20

申请人： Tzyy-Jang Tseng ,  Shu-Sheng Chiang ,  Tsung-Yuan Chen

发明人： Tzyy-Jang Tseng ,  Shu-Sheng Chiang ,  Tsung-Yuan Chen

IPC分类号： H01K3/10

CPC分类号： H05K1/115 ,  H05K1/0298 ,  H05K3/107 ,  H05K3/421 ,  H05K2201/0376 ,  H05K2203/1476 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49165

摘要： A circuit board including a circuit substrate, a dielectric layer, a first conductive layer and a second conductive layer is provided. The circuit substrate has a first surface and a first circuit layer. The dielectric layer is disposed on the circuit substrate and covers the first surface and the first circuit layer. The dielectric layer has a second surface, at least a blind via extended from the second surface to the first circuit layer and an intaglio pattern. The first conductive layer is disposed inside the blind via. The second conductive layer is disposed in the intaglio pattern and the blind via and covers the first conductive layer. The second conductive layer is electrically connected with the first circuit layer through the first conductive layer.

摘要翻译： 提供了包括电路基板，电介质层，第一导电层和第二导电层的电路板。 电路基板具有第一表面和第一电路层。 电介质层设置在电路基板上并覆盖第一表面和第一电路层。 电介质层具有第二表面，至少从第二表面延伸到第一电路层的盲孔和凹版图案。 第一导电层设置在盲孔内。 第二导电层设置在凹版图案和盲孔中并覆盖第一导电层。 第二导电层通过第一导电层与第一电路层电连接。

公开(公告)号：US08563363B2

公开(公告)日：2013-10-22

申请号：US13590847

申请日：2012-08-21

申请人： Tzyy-Jang Tseng ,  Chin-Sheng Wang ,  Chih-Hong Chuang

发明人： Tzyy-Jang Tseng ,  Chin-Sheng Wang ,  Chih-Hong Chuang

IPC分类号： H01L21/00

CPC分类号： H01L23/498 ,  H01L23/13 ,  H01L23/3677 ,  H01L23/3731 ,  H01L23/3732 ,  H01L23/562 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/32257 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/83001 ,  H01L2224/92247 ,  H01L2924/01019 ,  H01L2924/12042 ,  H01L2924/351 ,  H01L2924/00012 ,  H01L2924/00

摘要： A fabricating method of a semiconductor package structure is provided. A dielectric layer having a first surface and a second surface is provided. A patterned metal layer has been formed on the first surface of the dielectric layer. An opening going through the first and the second surfaces is formed. A carrier having a third surface and a fourth surface is formed at the second surface. A portion of the third surface is exposed by the opening of the dielectric layer. A semiconductor die having a joining surface and a side-surface is joined in the opening. At least a through hole going through the third and the fourth surfaces is formed. A metal layer having at least a heat conductive post extending from the fourth surface of the carrier to the through hole and disposed in the through hole and a containing cavity is formed on the fourth surface.

摘要翻译： 提供一种半导体封装结构的制造方法。 提供具有第一表面和第二表面的电介质层。 已经在介电层的第一表面上形成图案化的金属层。 形成穿过第一和第二表面的开口。 具有第三表面和第四表面的载体形成在第二表面。 第三表面的一部分被电介质层的开口暴露。 具有接合表面和侧表面的半导体管芯连接在开口中。 至少形成穿过第三和第四表面的通孔。 至少具有从载体的第四表面延伸到通孔并且设置在通孔中的导热柱和在第四表面上形成容纳腔的金属层。

公开(公告)号：US08390013B2

公开(公告)日：2013-03-05

申请号：US12915514

申请日：2010-10-29

申请人： Tzyy-Jang Tseng ,  Chin-Sheng Wang ,  Chih-Hong Chuang

发明人： Tzyy-Jang Tseng ,  Chin-Sheng Wang ,  Chih-Hong Chuang

IPC分类号： H01L33/00

CPC分类号： H01L23/498 ,  H01L23/13 ,  H01L23/3677 ,  H01L23/3731 ,  H01L23/3732 ,  H01L23/562 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/32257 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/83001 ,  H01L2224/92247 ,  H01L2924/01019 ,  H01L2924/12042 ,  H01L2924/351 ,  H01L2924/00012 ,  H01L2924/00

摘要： A semiconductor package structure includes a dielectric layer, a patterned metal layer, a carrier, a metal layer and a semiconductor die. The dielectric layer has a first surface, a second surface and an opening. The patterned metal layer is disposed on the first surface. The carrier is disposed at the second surface and has a third surface, a fourth surface and at least a through hole. A portion of the third surface and the through hole are exposed by the opening. The metal layer is disposed on the fourth surface and has a containing cavity and at least a heat conductive post extending from the fourth surface and disposed in the through hole. An end of the heat conductive post protrudes away from the third surface, and the containing cavity is located on the end of the heat conductive post. The semiconductor die is located in the containing cavity.

摘要翻译： 半导体封装结构包括电介质层，图案化金属层，载体，金属层和半导体管芯。 电介质层具有第一表面，第二表面和开口。 图案化的金属层设置在第一表面上。 载体设置在第二表面，并具有第三表面，第四表面和至少一个通孔。 第三表面和通孔的一部分由开口露出。 金属层设置在第四表面上，并且具有容纳腔和至少从第四表面延伸并设置在通孔中的导热柱。 导热柱的端部从第三表面突出，并且容纳腔位于导热柱的端部上。 半导体管芯位于容纳腔中。