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25 条记录 (耗时 0.02 秒)

    Method of making substrate member having electrical lines and apertured insulating film
    3.
    发明授权
    Method of making substrate member having electrical lines and apertured insulating film 失效
    制造具有电线和多孔绝缘膜的基片部件的方法

    公开(公告)号：US5517756A

    公开(公告)日：1996-05-21

    申请号：US247538

    申请日：1994-05-23

    申请人： Masaharu Shirai ,  Kimihiro Yamanaka

    发明人： Masaharu Shirai ,  Kimihiro Yamanaka

    IPC分类号： H01L21/48 ,  H01L23/538 ,  H05K1/11 ,  H05K3/34 ,  H05K3/02

    CPC分类号： H01L23/5386 ,  H01L21/4846 ,  H05K3/3452 ,  H01L2924/0002 ,  H05K1/117 ,  H05K2201/0989 ,  H05K2201/099 ,  Y10T29/49155 ,  Y10T29/49156

    摘要： In a substrate member (e.g., circuit board), a plurality of openings (15) are formed in an insulating film (14) which covers electric lines (12) formed on a substrate 11, with pad constructing (contacting) portions (13) of selected ones of the electric lines being exposed. In one example, the pad constructing portion (that portion of the pad to which final connection is to occur, e.g., by solder to a semiconductor device), is set to a first dimension (e.g., length) having a dimension less than a corresponding dimension of the original length. The film openings are also set to another dimension having an allowance size larger than a corresponding dimension of the pad constructing portion. The opening is thus of sufficiently large size in comparison to the respective pad being exposed so as to assure effective tolerance compensation for film positioning deviations in at least two (e.g., X and Y) directions as might occur during production of the substrate member.

    摘要翻译： 在衬底构件（例如电路板）中，在覆盖形成在衬底11上的电线（12）的绝缘膜（14）中形成多个开口（15），衬垫构成（接触）部分（13） 所选择的电线被暴露。 在一个示例中，焊盘构造部分（即将要发生最终连接的焊盘的部分，例如通过焊料发生到半导体器件）被设置为具有小于对应的尺寸的第一尺寸（例如，长度） 尺寸原始长度。 薄膜开口也被设定为具有比垫构成部分的对应尺寸大的容许尺寸的另一尺寸。 因此，与相应的衬垫相比，开口的尺寸足够大，以便确保在衬底构件的制造期间可能发生的至少两个（例如，X和Y）方向上的膜定位偏差的有效的公差补偿。

    Substrate member having electric lines and apertured insulating film
    4.
    发明授权
    Substrate member having electric lines and apertured insulating film 失效
    具有电线和多孔绝缘膜的基片部件

    公开(公告)号：US5252781A

    公开(公告)日：1993-10-12

    申请号：US859750

    申请日：1992-03-30

    申请人： Masaharu Shirai ,  Kimihiro Yamanaka

    发明人： Masaharu Shirai ,  Kimihiro Yamanaka

    IPC分类号： H01L21/48 ,  H01L23/538 ,  H05K1/11 ,  H05K3/34 ,  H05K1/00

    CPC分类号： H01L23/5386 ,  H01L21/4846 ,  H05K3/3452 ,  H01L2924/0002 ,  H05K1/117 ,  H05K2201/0989 ,  H05K2201/099 ,  Y10T29/49155 ,  Y10T29/49156

    摘要： In a substrate member (e.g., circuit board), a plurality of openings (15) are formed in an insulating film (14) which covers electric lines (12) formed on a substrate 11, with pad constructing (contacting) portions (13) of selected ones of the electric lines being exposed. In one example, the pad constructing portion (that portion of the pad to which final connection is to occur, e.g., by solder to a semiconductor device), is set to a first dimension (e.g., length) having a dimension less than a corresponding dimension of the original length. The film openings are also set to another dimension having an allowance size larger than a corresponding dimension of the pad constructing portion. The opening is thus of sufficiently large size in comparison to the respective pad being exposed so as to assure effective tolerance compensation for film positioning deviations in at least two (e.g., X and Y) directions as might occur during production of the substrate member.

    Manufacturing process for organic chip carrier
    9.
    发明授权
    Manufacturing process for organic chip carrier 失效
    有机芯片载体制造工艺

    公开(公告)号：US5784781A

    公开(公告)日：1998-07-28

    申请号：US559214

    申请日：1995-11-16

    申请人： Masaharu Shirai ,  Kenji Terada ,  Yutaka Tsukada ,  Shuhei Tsuchita

    发明人： Masaharu Shirai ,  Kenji Terada ,  Yutaka Tsukada ,  Shuhei Tsuchita

    IPC分类号： H01L21/28 ,  H01L21/48 ,  H01L21/768 ,  H01L23/522 ,  H05K3/00 ,  H05K3/46 ,  H05K1/14

    CPC分类号： H01L21/486 ,  H05K3/0023 ,  H05K2201/09827 ,  H05K2203/025 ,  H05K3/0044 ,  H05K3/4644 ,  Y10T29/49155 ,  Y10T29/49165

    摘要： A manufacturing process for an organic chip carrier is disclosed which permits one to form a substantially bowl-shaped via hole in the substrate of the chip carrier, which makes it easy to deposit a conductive layer having a substantially uniform thickness on the sidewall of the via hole. In accordance with the manufacturing process, photosensitive resin 3 is provided on a substrate 1 in a thickness which is the thickness necessary for a final insulating layer plus a thickness to be removed by, for example grinding, the photosensitive resin 3. Cavities are then formed in the photosensitive resin 3 in a predetermined pattern by exposure and development. The photosensitive resin 3 formed with the cavities 8 is heat-cured. Subsequently, when the photo-cured layer 6a and a part of the heat-cured layer 3a are removed, e.g., ground off, a substantially bowl-shaped via hole 9 is formed.

    摘要翻译： 公开了一种用于有机芯片载体的制造方法，其可以在芯片载体的基板中形成基本上碗状的通孔，这使得容易将具有基本均匀厚度的导电层沉积在通孔的侧壁上 孔。 根据制造方法，感光性树脂3以通过例如研磨感光性树脂3除去最终绝缘层加上除去厚度的厚度设置在基板1上。然后形成凹部 通过曝光和显影以预定图案形成感光性树脂3。 形成有空腔8的感光性树脂3被热固化。 随后，当光固化层6a和热固化层3a的一部分被去除时，例如研磨掉，形成大致碗状的通孔9。

    Method for fabricating a chip carrier with migration barrier, and resulating chip carrier
    10.
    发明授权
    Method for fabricating a chip carrier with migration barrier, and resulating chip carrier 失效
    制造具有迁移屏障的芯片载体的方法，以及所得到的芯片载体

    公开(公告)号：US5776662A

    公开(公告)日：1998-07-07

    申请号：US647513

    申请日：1996-05-14

    申请人： Masaharu Shirai ,  Yutaka Tsukada

    发明人： Masaharu Shirai ,  Yutaka Tsukada

    IPC分类号： G03F7/11 ,  H01L21/48 ,  H01L23/498 ,  H01L23/538 ,  H05K1/03 ,  H05K3/00 ,  H05K3/46 ,  G03C5/00 ,  H05K7/00

    CPC分类号： H01L21/4857 ,  H01L23/49822 ,  H01L23/49894 ,  H01L23/5383 ,  H05K3/0023 ,  H01L2924/0002 ,  H05K2201/0195 ,  H05K2203/025 ,  H05K3/0044 ,  H05K3/4644

    摘要： To inhibit the migration of conductive layers in a multilayer chip carrier, e.g., a multilayer printed circuit board, an optically cured layer 13, which is an anti-migration layer, is formed in an insulating layer 12 located between a first conductive layer 8 and a second conductive layer 6. Such a structure is formed by thinning, e.g., grinding down, a first insulating layer, leaving about half the thickness of the first insulating layer. This first insulating layer is selectively optically irradiated with actinic radiation to form an optically cured layer. Via holes are etched into the non-irradiated portions of the first insulating layer. Thereafter, a second insulating layer is formed on the first insulating layer, and it too is selectively optically irradiated with actinic radiation. Via holes are etched into the non-irradiated portions of the second insulating layer, directly over the via holes in the first insulating layer, and the second insulating layer is also thinned.

    摘要翻译： 为了抑制多层芯片载体（例如多层印刷电路板）中的导电层的迁移，作为抗迁移层的光固化层13形成在位于第一导电层8和 第二导电层6.这种结构通过使第一绝缘层的厚度留下约一半的方式，使第一绝缘层变薄（例如，研磨）而形成。 选择性地用光化辐射照射第一绝缘层以形成光固化层。 通孔蚀刻到第一绝缘层的未照射部分中。 此后，在第一绝缘层上形成第二绝缘层，并且还用光化辐射选择性地光照射。 通孔直接蚀刻到第二绝缘层的未照射部分中，直接在第一绝缘层中的通孔上方，并且第二绝缘层也变薄。