公开(公告)号：US5018001A

公开(公告)日：1991-05-21

申请号：US442669

申请日：1989-11-29

申请人： Kenji Kondo ,  Kazuo Akamatsu ,  Takeshi Yamauchi ,  Tooru Yamaoka ,  Atsushi Komura

发明人： Kenji Kondo ,  Kazuo Akamatsu ,  Takeshi Yamauchi ,  Tooru Yamaoka ,  Atsushi Komura

IPC分类号： H01L23/52 ,  H01L21/28 ,  H01L21/285 ,  H01L21/3205 ,  H01L23/532

CPC分类号： H01L23/53223 ,  H01L23/53219 ,  H01L2924/0002

摘要： An aluminum line including nitrogen formed as a film in a semiconductor integrated circuit is disclosed. Each crystal grain size of the aluminum line is lower than or equal to 0.3 .mu.m to suppress electromigration. A method of forming the aluminum line which can supress electromigration is also disclosed. The amount of an inert gas Q and the amount of a nitrogen gas Q.sub.N are controlled to satisfy "2.ltoreq.(Q.sub.N /Q).times.100.ltoreq.10".

摘要翻译： 公开了一种包括在半导体集成电路中形成为膜的氮的铝线。 铝线的每个晶粒尺寸小于或等于0.3μm以抑制电迁移。 还公开了一种能够抑制电迁移的铝线的形成方法。 控制惰性气体量Q和氮气量QN以满足“2 <=（QN / Q）×100

公开(公告)号：US6066891A

公开(公告)日：2000-05-23

申请号：US802214

申请日：1997-02-19

申请人： Tooru Yamaoka ,  Atsushi Komura ,  Takeshi Yamauchi ,  Yoshihiko Isobe ,  Hiroyuki Yamane

发明人： Tooru Yamaoka ,  Atsushi Komura ,  Takeshi Yamauchi ,  Yoshihiko Isobe ,  Hiroyuki Yamane

IPC分类号： H01L21/285 ,  H01L21/768 ,  H01L29/45 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L21/76867 ,  H01L21/28518 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76858 ,  H01L23/53223 ,  H01L29/456 ,  H01L2924/0002

摘要： The purpose of the present invention is to obtain an electrode wiring structure for semiconductor devices that can suppress the occurrence of Al voids inside aluminum alloy wiring without regard to the orientation of such aluminum alloy wiring. An interlayer insulator film 11, a titanium layer 12, a titanium nitride layer 13 that serves as the barrier layer, an aluminum alloy wiring layer 15 and a protective film 18 are formed on top of the silicon substrate 10 to compose the electrode structure. In this case, a distortion relaxation layer 14, with a film thickness of approximately over 10 nm and which is an intermetallic compound that includes aluminum and titanium in its composition, is formed in between the titanium nitride layer 13 and the aluminum alloy wiring layer 15. Because of this distortion relaxation layer, for every wiring width of 1 .mu.m, the number of Al voids with widths of over 0.3 .mu.m is practically reduced to 0.

摘要翻译： 本发明的目的是为了获得能够抑制铝合金布线内的Al空隙的出现而不考虑这种铝合金布线的取向的半导体器件的电极布线结构。 在硅衬底10的顶部上形成层间绝缘膜11，钛层12，用作阻挡层的氮化钛层13，铝合金布线层15和保护膜18，以构成电极结构。 在这种情况下，在氮化钛层13和铝合金布线层15之间形成膜厚约为10nm以上的构成铝和钛的金属间化合物的失真弛豫层14 由于这种失真弛豫层，对于1μm的每个布线宽度，宽度大于0.3μm的Al空隙的数量实际上减少到0。

公开(公告)号：US06348735B1

公开(公告)日：2002-02-19

申请号：US09482895

申请日：2000-01-14

申请人： Tooru Yamaoka ,  Atsushi Komura ,  Takeshi Yamauchi ,  Yoshihiko Isobe ,  Hiroyuki Yamane

发明人： Tooru Yamaoka ,  Atsushi Komura ,  Takeshi Yamauchi ,  Yoshihiko Isobe ,  Hiroyuki Yamane

IPC分类号： H01L2348

CPC分类号： H01L21/76867 ,  H01L21/28518 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76858 ,  H01L23/53223 ,  H01L29/456 ,  H01L2924/0002 ,  H01L2924/00

摘要： The purpose of the present invention is to obtain an electrode wiring structure for semiconductor devices that can suppress the occurrence of Al voids inside aluminum alloy wiring without regard to the orientation of such aluminum alloy wiring. An interlayer insulator film 11, a titanium layer 12, a titanium nitride layer 13 that serves as the barrier layer, an aluminum alloy wiring layer 15 and a protective film 18 are formed on top of the silicon substrate 10 to compose the electrode structure. In this case, a distortion relaxation layer 14, with a film thickness of approximately over 10 nm and which is an intermetallic compound that includes aluminum and titanium in its composition, is formed in between the titanium nitride layer 13 and the aluminum alloy wiring layer 15. Because of this distortion relaxation layer, for every wiring width of 1 &mgr;m, the number of Al voids with widths of over 0.3 &mgr;m is practically reduced to 0.

摘要翻译： 本发明的目的是为了获得能够抑制铝合金布线内的Al空隙的出现而不考虑这种铝合金布线的取向的半导体器件的电极布线结构。 在硅衬底10的顶部上形成层间绝缘膜11，钛层12，用作阻挡层的氮化钛层13，铝合金布线层15和保护膜18，以构成电极结构。 在这种情况下，在氮化钛层13和铝合金布线层15之间形成膜厚约为10nm以上的构成铝和钛的金属间化合物的失真弛豫层14 由于该失真弛豫层，对于1mum的每个布线宽度，宽度大于0.3μm的Al空隙的数量实际上减小到0。

公开(公告)号：US5522966A

公开(公告)日：1996-06-04

申请号：US152895

申请日：1993-11-17

申请人： Atsushi Komura ,  Yoshikazu Sakano ,  Kenji Kondo ,  Keiichi Kon ,  Tetsuhiko Sanbei ,  Shoji Miura

发明人： Atsushi Komura ,  Yoshikazu Sakano ,  Kenji Kondo ,  Keiichi Kon ,  Tetsuhiko Sanbei ,  Shoji Miura

IPC分类号： H01L21/302 ,  H01L21/3065 ,  H01L21/00

CPC分类号： H01L21/3065 ,  Y10S438/906

摘要： A process for forming trenches on a surface of a semiconductor substrate by dry etching using a gas mixture. The gas mixture comprises; (1) an etchant gas comprising at least bromine which etches the semiconductor surface to form trenches, (2) a cleaning gas comprising a halogen which evaporates residue formed by the etching, and (3) a reactive gas, e.g. N.sub.2, capable of reacting with material formed during the etching and capable of controlling the inclination of the trenches.

摘要翻译： 一种通过使用气体混合物的干蚀刻在半导体衬底的表面上形成沟槽的工艺。 气体混合物包括： （1）至少包含溴的蚀刻剂气体，蚀刻半导体表面以形成沟槽，（2）包含卤素的清洁气体，其蒸发由蚀刻形成的残余物，和（3）反应性气体，例如， N2，能够与蚀刻期间形成的材料反应并且能够控制沟槽的倾斜度。

公开(公告)号：US5423941A

公开(公告)日：1995-06-13

申请号：US152896

申请日：1993-11-17

申请人： Atsushi Komura ,  Yoshikazu Sakano ,  Kenji Kondo ,  Keiichi Kon ,  Tetsuhiko Sanbei ,  Shoji Miura

发明人： Atsushi Komura ,  Yoshikazu Sakano ,  Kenji Kondo ,  Keiichi Kon ,  Tetsuhiko Sanbei ,  Shoji Miura

IPC分类号： H01L21/302 ,  H01L21/3065 ,  C23F1/00

CPC分类号： H01L21/3065

摘要： A process for forming deep trenches on a surface of a semiconductor substrate by forming a mask on the surface of the semiconductor, which prescribes the position of the trenches; and then dry etching the semiconductor surface using a gas mixture comprising (1) an etchant, bromine containing, gas which etches the semiconductor surface to form trenches, (2) a cleaning, halogen containing, gas which evaporates the residue formed by the etching; and (3) a reactive gas capable of reacting with material formed during the etching and capable of decreasing the wastage of the mask by the etchant gas.

摘要翻译： 一种通过在半导体的表面上形成掩模来形成半导体衬底的表面上的深沟槽的方法，其规定了沟槽的位置; 然后使用气体混合物干燥蚀刻半导体表面，所述气体混合物包括（1）蚀刻剂，含溴的气体，蚀刻半导体表面以形成沟槽，（2）清洁，含卤素的气体，其蒸发由蚀刻形成的残余物; 和（3）能够与在蚀刻期间形成的材料反应的反应气体，并且能够通过蚀刻剂气体减少掩模的浪费。

公开(公告)号：US20070111478A1

公开(公告)日：2007-05-17

申请号：US11600136

申请日：2006-11-16

申请人： Atsushi Komura ,  Muneo Tamura ,  Kazuhiko Sugiura ,  Hirotsugu Funato ,  Yumi Maruyama ,  Tetsuo Fujii ,  Kenji Kohno

发明人： Atsushi Komura ,  Muneo Tamura ,  Kazuhiko Sugiura ,  Hirotsugu Funato ,  Yumi Maruyama ,  Tetsuo Fujii ,  Kenji Kohno

IPC分类号： H01L21/00

CPC分类号： B23K26/40 ,  B23K26/53 ,  B23K2101/40 ,  B23K2103/50 ,  B28D5/0011 ,  H01L21/78

摘要： A method for dicing a semiconductor substrate includes: forming a reforming layer in the substrate by irradiating a laser beam on the substrate; forming a groove on the substrate along with a cutting line; and applying a force to the substrate in order to cutting the substrate at the reforming layer as a starting point of cutting. The groove has a predetermined depth so that the groove is disposed near the reforming layer, and the force provides a stress at the groove.

摘要翻译： 一种用于切割半导体衬底的方法包括：通过在衬底上照射激光束在衬底中形成重整层; 与切割线一起在基板上形成凹槽; 并向基板施加力以切割重整层处的基板作为切割的起点。 槽具有预定的深度，使得槽设置在重整层附近，并且该力在槽处提供应力。

公开(公告)号：US07642653B2

公开(公告)日：2010-01-05

申请号：US11976308

申请日：2007-10-23

申请人： Takeshi Kuzuhara ,  Atsushi Komura ,  Mitsutaka Katada ,  Takayoshi Naruse

发明人： Takeshi Kuzuhara ,  Atsushi Komura ,  Mitsutaka Katada ,  Takayoshi Naruse

IPC分类号： H01L23/52 ,  H01L23/48 ,  H01L29/40 ,  H01L29/00 ,  H01L21/4763

CPC分类号： H01L21/76838 ,  H01L23/5283 ,  H01L23/53238 ,  H01L24/03 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05006 ,  H01L2224/05082 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05187 ,  H01L2224/05554 ,  H01L2224/05572 ,  H01L2224/05611 ,  H01L2224/05616 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48463 ,  H01L2224/48611 ,  H01L2224/48616 ,  H01L2224/48624 ,  H01L2224/48639 ,  H01L2224/48644 ,  H01L2224/49111 ,  H01L2224/85205 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01068 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/19043 ,  H01L2924/20753 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2924/01204 ,  H01L2924/013 ,  H01L2924/00013

摘要： A semiconductor device includes a substrate, an element formed in the substrate, an insulation film formed on the substrate, wiring layers, and an electrode pad. The wiring layers are multilayered and electrically coupled to the element through the insulation film. The electrode pad is electrically coupled to a top wiring layer of the wiring layers. The top wiring layer is configured to be a top wiring-electrode layer that doubles as an electrode layer disposed under the electrode pad. The electrode layer of the top wiring-electrode layer is disposed directly above the element. The electrode pad and the electrode layer are multilayered to form a pad structure.

摘要翻译： 半导体器件包括衬底，形成在衬底中的元件，形成在衬底上的绝缘膜，布线层和电极焊盘。 布线层是多层的，并通过绝缘膜与元件电耦合。 电极焊盘电连接到布线层的顶部布线层。 顶部布线层被配置为作为布置在电极焊盘下方的电极层的顶部布线电极层。 顶部布线电极层的电极层设置在元件的正上方。 电极焊盘和电极层是多层的以形成焊盘结构。

公开(公告)号：US20070111390A1

公开(公告)日：2007-05-17

申请号：US11598654

申请日：2006-11-14

申请人： Atsushi Komura ,  Tetsuo Fujii ,  Muneo Tamura ,  Makoto Asai

发明人： Atsushi Komura ,  Tetsuo Fujii ,  Muneo Tamura ,  Makoto Asai

IPC分类号： H01L21/00 ,  H01L23/02

CPC分类号： H01L21/67132 ,  B23K26/009 ,  B23K26/40 ,  B23K26/53 ,  B23K2101/40 ,  B23K2103/50 ,  B28D5/0011 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/3192 ,  H01L2221/68327 ,  H01L2221/68336 ,  H01L2924/0002 ,  H01L2924/19041 ,  H01L2924/00

摘要： A device separated from a wafer includes: a chip having a sidewall, which is provided by a dicing surface of the wafer in a case where the device is separated from the wafer; and a protection member disposed on the sidewall of the chip for protecting the chip from being contaminated by a dust from the dicing surface. In the device, the dicing surface of the wafer is covered with the protection member so that the chip is prevented from contaminated with the dust.

摘要翻译： 与晶片分离的器件包括：具有侧壁的芯片，其在器件与晶片分离的情况下由晶片的切割表面提供; 以及设置在芯片的侧壁上的保护构件，用于保护芯片免受来自切割表面的灰尘的污染。 在该装置中，晶片的切割面被保护部件覆盖，从而防止芯片被灰尘污染。

公开(公告)号：US5480832A

公开(公告)日：1996-01-02

申请号：US75514

申请日：1993-10-21

申请人： Shoji Miura ,  Takayuki Sugisaka ,  Atsushi Komura ,  Toshio Sakakibara

发明人： Shoji Miura ,  Takayuki Sugisaka ,  Atsushi Komura ,  Toshio Sakakibara

IPC分类号： H01L21/762 ,  H01L21/763 ,  H01L21/768 ,  H01L21/76

CPC分类号： H01L21/763 ,  H01L21/76264 ,  H01L21/76802 ,  H01L21/76275 ,  H01L21/76281 ,  H01L21/76286 ,  Y10S148/05 ,  Y10S148/135 ,  Y10S438/977

摘要： An object of the invention is to prevent the occurrence of breaking or short-circuiting of a wiring caused by a difference in level in an isolation trench area formed in an SOI substrate. An oxide film is formed for a pad on the main surface of an SOI layer formed on an insulating substrate, a silicon nitride film are formed and an SiO.sub.2 film in order, then an isolation trench reaching to the insulating substrate is by means of an R.I.E process using the SiO.sub.2 film as a mask. Thereafter an insulating film is formed on an inside wall of the isolation trench by means of thermal oxidation, the isolation trench is filled with polysilicon, the polysilicon is etched back while controlling the etching so that the top of the polysilicon in the isolation trench remains higher than the top of the silicon nitride film, an extra part of the polysilicon deposited on the surface of the substrate, is removed and then the SiO.sub.2 film used as a mask when forming the isolation trench is etched off using the polysilicon in the isolation trench and the silicon nitride film as an etching stopper. In this manner, since the SiO.sub.2 film used as a mask is etched off after filling the isolation trench with polysilicon, the oxide film for isolating between the substrates is not etched when removing the mask film. Moreover since the polysilicon is the isolation trench and the silicon nitride film act as an etching stopper when etching off the SiO.sub.2 film used as a mask, the oxide film for a pad existing thereunder and the insulating film formed on an inside wall of the trench can also be prevented from being etched and a flatness at an isolation trench area is not deteriorated.

摘要翻译： PCT No.PCT / JP92 / 01326 Sec。 371日期：1993年10月21日 102（e）日期1993年10月21日PCT提交1992年10月12日PCT公布。 公开号WO93 / 08596 日期：1993年04月29日。本发明的目的在于防止在SOI衬底中形成的隔离沟槽区域中的电平差引起的布线断裂或短路。 在绝缘基板上形成的SOI层的主表面上形成氧化膜，依次形成氮化硅膜和SiO 2膜，然后通过RIE到达绝缘基板的隔离沟槽 使用SiO 2膜作为掩模。 此后，通过热氧化在隔离沟槽的内壁上形成绝缘膜，隔离沟槽填充有多晶硅，在控制蚀刻的同时蚀刻多晶硅，使得隔离沟槽中的多晶硅的顶部保持较高 除去氮化硅膜的顶部，去除沉积在衬底表面上的多晶硅的额外部分，然后使用隔离沟槽中的多晶硅蚀刻掉形成隔离沟槽时用作掩模的SiO 2膜， 作为蚀刻停止层的氮化硅膜。 以这种方式，由于在用多晶硅填充隔离沟槽之后蚀刻用作掩模的SiO 2膜，因此在去除掩模膜时不会蚀刻用于隔离的氧化膜。 此外，由于多晶硅是隔离沟槽，并且氮化硅膜在蚀刻掉用作掩模的SiO 2膜时用作蚀刻阻挡层，所以存在于其上的垫的氧化膜和形成在沟槽的内壁上的绝缘膜 也防止蚀刻，并且隔离沟槽区域的平坦度不会劣化。

公开(公告)号：US08007561B2

公开(公告)日：2011-08-30

申请号：US11917472

申请日：2006-06-13

申请人： Tomoaki Shindo ,  Atsushi Komura ,  Hiroaki Takashima ,  Toshiyuki Taniuchi ,  Masafumi Fukumura ,  Kei Takahashi

发明人： Tomoaki Shindo ,  Atsushi Komura ,  Hiroaki Takashima ,  Toshiyuki Taniuchi ,  Masafumi Fukumura ,  Kei Takahashi

IPC分类号： C22C29/04

CPC分类号： C22C29/04 ,  B22F2005/001 ,  B22F2998/10 ,  B22F2999/00 ,  C22C27/04 ,  Y10T407/1924 ,  Y10T407/22 ,  Y10T407/27 ,  B22F3/02 ,  B22F3/10 ,  B22F2201/20 ,  B22F2201/11 ,  B22F2201/02

摘要： A cermet insert having a structure composed of a hard phase and a binding phase and, as a sintered body composition, containing Ti, Nb and/or Ta, and W in a total amount of Ti in terms of carbonitride, Nb and/or Ta in terms of carbide and W in terms of carbide of 70 to 95 wt. % of an entirety of the microstructure, and containing W in terms of carbide in an amount of 15 to 35 wt. % of the entirety of the microstructure, the sintered body composition further containing Co and/or Ni. The hard phase has one or two or more of the phases: (1) a first hard phase of a core-having structure whose core portion contains a titanium carbonitride phase and a peripheral portion containing a (Ti, W, Ta/Nb)CN phase, (2) a second hard phase of a core-having structure whose core portion and peripheral portion both contain a (Ti, W, Ta/Nb)CN phase, and (3) a third hard phase of single-phase structure including a titanium cabonitride phase. Moreover, the titanium carbonitride phase includes a W-rich phase unevenly distributed in the titanium carbonitride phase.

摘要翻译： 具有由硬质相和结合相构成的结构的金属陶瓷插入体，作为烧结体组合物，以碳氮化物，Nb和/或Ta为基准，含有Ti，Nb和/或Ta的总和量为Ti 以碳化物计，W为70〜95重量％。 微观结构的整体的％，以碳化物计，W为15〜35重量％。 微结构整体的％，烧结体组合物还含有Co和/或Ni。 硬相具有一个或两个以上的相：（1）核心部分含有碳氮化钛相的核心结构的第一硬质相和包含（Ti，W，Ta / Nb）CN （2）具有核心部分和周边部分都包含（Ti，W，Ta / Nb）CN相的核心结构的第二硬相，和（3）第三硬相的单相结构，包括 钛白云母相。 此外，碳氮化钛相包括不均匀分布在碳氮化钛相中的富W相。