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129 条记录 (耗时 0.018 秒)

    Radio communication apparatus
    1.
    发明授权
    Radio communication apparatus 失效
    无线通信装置

    公开(公告)号：US5610946A

    公开(公告)日：1997-03-11

    申请号：US378337

    申请日：1995-01-26

    申请人： Kiyoshi Tanaka ,  Ping Huang

    发明人： Kiyoshi Tanaka ,  Ping Huang

    IPC分类号： H04L27/02 ,  H04B1/16 ,  H04J1/00 ,  H04J1/05 ,  H04L27/18 ,  H04J9/00 ,  H04L27/06 ,  H04L27/32

    CPC分类号： H04L27/18 ,  H04J1/05

    摘要： A radio communication apparatus comprises a first/second modulator for modulating a first/second signal according to a first/second frequency, a first demodulator for detecting the received first modulation signal and regenerating the carrier, a clock regenerator for regenerating a clock from the detection output from the first demodulator, an amplitude sampler for sampling the amplitude of the received first modulation signal according to the regenerated clock, a second demodulator for controlling the frequency of the received second modulation signal and executing demodulation for the signal, and a gain controller for executing gain control for the output from the second demodulator according to the output from the amplitude sampler.

    摘要翻译： 一种无线电通信装置，包括用于根据第一/第二频率调制第一/第二信号的第一/第二调制器，用于检测所接收的第一调制信号并再生载波的第一解调器，用于从检测中再生时钟的时钟再生器 从所述第一解调器输出的振幅采样器，用于根据所述再生时钟对所接收的第一调制信号的振幅进行采样的振幅采样器，用于控制所接收的第二调制信号的频率并执行所述信号的解调的第二解调器， 根据振幅采样器的输出对第二解调器的输出执行增益控制。

    Method of correcting carrier leak in a transmitter
    2.
    发明授权
    Method of correcting carrier leak in a transmitter 失效
    校正发射机载波泄漏的方法

    公开(公告)号：US5574994A

    公开(公告)日：1996-11-12

    申请号：US379810

    申请日：1995-01-27

    申请人： Ping Huang ,  Yumi Hachisuka ,  Kiyoshi Tanaka

    发明人： Ping Huang ,  Yumi Hachisuka ,  Kiyoshi Tanaka

    IPC分类号： H04J11/00 ,  H01Q3/26 ,  H04B1/04 ,  H04L27/00 ,  H01Q11/12

    CPC分类号： H01Q3/26

    摘要： A method of suppressing generation of carrier leak in a transmitter and reducing deterioration of communication quality comprises the steps of outputting DC elements (I, Q) from a DSP gradually changing the voltage values, measuring a sum of the DC elements (.DELTA.I.sub.DC, .DELTA.Q.sub.DC) and DC elements (I, Q), storing the DC elements (I, Q), when the above sum is equal to a specified value (herein, 0 V), as DC elements -.DELTA.I.sub.DC, -.DELTA.Q.sub.DC for correction, and correcting the DC elements (I.sub.DC, Q.sub.DC) (DC elements obtained by amplifying DC elements for (I, Q) channels demodulated by a quadrature demodulator during transmission) using the DC elements (-.DELTA.I.sub.DC, -.DELTA.Q.sub.DC) for correction during transmission.

    摘要翻译： 一种抑制发送器中的载波泄漏的产生并减少通信质量恶化的方法包括以下步骤：从DSP逐渐改变电压值输出DC元件（I，Q），测量直流元件的总和（DELTA IDC，DELTA QDC）和DC元件（I，Q），当上述和等于指定值（这里为0V）时，存储DC元件（I，Q）作为DC元件-DDTA IDC，DELTA QDC用于校正， 并且通过使用DC元件（-TATA IDC，-TATAQDC）来校正DC元件（IDC，QDC）（通过在发送期间由正交解调器解调的（I，Q）信道的DC元件）获得的DC元件） 。

    PACKAGING METHOD OF MOLDED WAFER LEVEL CHIP SCALE PACKAGE (WLCSP)
    6.
    发明申请
    PACKAGING METHOD OF MOLDED WAFER LEVEL CHIP SCALE PACKAGE (WLCSP) 有权
    模压水平切片尺寸包装（WLCSP）的包装方法

    公开(公告)号：US20130210195A1

    公开(公告)日：2013-08-15

    申请号：US13547358

    申请日：2012-07-12

    申请人： Yan Xun Xue ,  Hamza Yilmaz ,  Yueh-Se Ho ,  Jun Lu ,  Ping Huang ,  Lei Shi ,  Lei Duan ,  Yuping Gong

    发明人： Yan Xun Xue ,  Hamza Yilmaz ,  Yueh-Se Ho ,  Jun Lu ,  Ping Huang ,  Lei Shi ,  Lei Duan ,  Yuping Gong

    IPC分类号： H01L21/78

    CPC分类号： H01L21/563 ,  H01L23/3157 ,  H01L2224/73104 ,  H01L2224/83191 ,  H01L2924/13091 ,  H01L2924/00

    摘要： A WLCSP method comprises: depositing a metal bump on bonding pads of chips; forming a first packaging layer at front surface of wafer to cover metal bumps while forming an un-covered ring at the edge of wafer to expose the ends of each scribe line located between two adjacent chips; thinning first packaging layer to expose metal bumps; forming a groove on front surface of first packaging layer along each scribe line by cutting along a straight line extended by two ends of scribe line exposed on front surface of un-covered ring; grinding back surface of wafer to form a recessed space and a support ring at the edge of the wafer; depositing a metal layer at bottom surface of wafer in recessed space; cutting off the edge portion of wafer; and separating individual chips from wafer by cutting through first packaging layer, the wafer and metal layer along groove.

    摘要翻译： WLCSP方法包括：在芯片的焊盘上沉积金属凸块; 在晶片的前表面形成第一包装层以覆盖金属凸块，同时在晶片边缘形成未覆盖的环，以露出位于两个相邻芯片之间的每个划线的端部; 稀释第一包装层以暴露金属凸块; 通过沿着未被覆盖的环的前表面上暴露的划线的两端延伸的直线切割沿着每个划线在第一包装层的前表面上形成凹槽; 研磨晶片的后表面以在晶片的边缘处形成凹陷空间和支撑环; 在凹陷空间中在晶片的底面沉积金属层; 切断晶片的边缘部分; 以及通过沿着沟槽切割第一包装层，晶片和金属层，从晶片分离单个芯片。

    WAFER LEVEL PACKAGING METHOD OF ENCAPSULATING THE BOTTOM AND SIDE OF A SEMICONDUCTOR CHIP
    8.
    发明申请
    WAFER LEVEL PACKAGING METHOD OF ENCAPSULATING THE BOTTOM AND SIDE OF A SEMICONDUCTOR CHIP 有权
    封装半导体芯片底部和底部的水平包装方法

    公开(公告)号：US20130095612A1

    公开(公告)日：2013-04-18

    申请号：US13273168

    申请日：2011-10-13

    申请人： Ping Huang ,  Ruisheng Wu ,  Lei Duan ,  Yi Chen ,  Yuping Gong

    发明人： Ping Huang ,  Ruisheng Wu ,  Lei Duan ,  Yi Chen ,  Yuping Gong

    IPC分类号： H01L21/82

    CPC分类号： H01L23/3171 ,  H01L21/568 ,  H01L23/3114 ,  H01L24/19 ,  H01L24/96 ,  H01L2224/02379 ,  H01L2224/12105 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/00

    摘要： A chip-scale packaging method, with bottom and side of a semiconductor chip encapsulated, includes the following steps: attaching backside of a thinned semiconductor wafer to a dicing tape; separating individual chips by cutting from front side of the wafer at scribe line but not cut through the dicing tape; flipping and attaching the wafer onto a top surface of a double-sided tape, then removing the dicing tape; attaching bottom surface of the double-sided tape on a supporting plate; filling the space between adjacent chips and covering the whole wafer backside with a molding material; flipping the whole structure and remove the supporting plate; placing solder balls at corresponding positions on electrodes of each chip and performing backflow treatment; finally separating individual chip packages by cutting through molding material at the space between adjacent chip packages with molding material encapsulating the bottom and side of each individual semiconductor chip.

    摘要翻译： 封装了半导体芯片的底部和侧面的芯片级封装方法包括以下步骤：将薄化的半导体晶片的背面安装到切割带上; 通过在切割线处切割晶片的正面而不切割切割带来分离各个芯片; 翻转并将晶片连接到双面胶带的顶表面上，然后移除切割胶带; 将双面胶带的底面附着在支撑板上; 填充相邻芯片之间的空间并用模制材料覆盖整个晶片背面; 翻转整个结构并拆下支撑板; 将焊球放置在每个芯片的电极上的相应位置，并执行回流处理; 最后通过在封装每个单独的半导体芯片的底部和侧面的成型材料之间切割相邻芯片封装之间的空间处的模制材料来分离单个芯片封装。