利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

21 条记录 (耗时 0.035 秒)

    CERAMIC ELECTRONIC COMPONENT AND MANUFACTURING METHOD THEREOF
    1.
    发明申请
    CERAMIC ELECTRONIC COMPONENT AND MANUFACTURING METHOD THEREOF 有权
    陶瓷电子元件及其制造方法

    公开(公告)号：US20130107420A1

    公开(公告)日：2013-05-02

    申请号：US13287253

    申请日：2011-11-02

    申请人： Kiyoyasu SAKURADA ,  Kota ZENZAI ,  Hisayoshi OMORI ,  Takashi KANAYAMA ,  Shinji OTANI ,  Naoki SHIMIZU ,  Seiji KATSUTA

    发明人： Kiyoyasu SAKURADA ,  Kota ZENZAI ,  Hisayoshi OMORI ,  Takashi KANAYAMA ,  Shinji OTANI ,  Naoki SHIMIZU ,  Seiji KATSUTA

    IPC分类号： H01G4/12 ,  H01G4/00

    CPC分类号： H01G4/2325 ,  H01G4/12 ,  H01G4/30

    摘要： A ceramic electronic component includes a ceramic body and an outer electrode. The outer electrode is disposed on the ceramic body. The outer electrode includes a first conductive layer and a second conductive layer. The first conductive layer includes a resin, a first metal component, and a second metal component having a higher melting point than the first metal component. The second conductive layer is disposed on the first conductive layer. The second conductive layer is includes a plating film. An alloy particle containing the first metal component and the second metal component protrudes to the second conductive layer side from a surface of the first conductive layer.

    摘要翻译： 陶瓷电子部件包括陶瓷体和外部电极。 外部电极设置在陶瓷体上。 外电极包括第一导电层和第二导电层。 第一导电层包括树脂，第一金属组分和具有比第一金属组分更高的熔点的第二金属组分。 第二导电层设置在第一导电层上。 第二导电层包括镀膜。 含有第一金属成分和第二金属成分的合金粒子从第一导电层的表面突出到第二导电层侧。

    CERAMIC ELECTRONIC COMPONENT AND MANUFACTURING METHOD THEREOF
    2.
    发明申请
    CERAMIC ELECTRONIC COMPONENT AND MANUFACTURING METHOD THEREOF 有权
    陶瓷电子元件及其制造方法

    公开(公告)号：US20130107421A1

    公开(公告)日：2013-05-02

    申请号：US13287276

    申请日：2011-11-02

    申请人： Kota ZENZAI ,  Hisayoshi OMORI ,  Takashi KANAYAMA ,  Kiyoyasu SAKURADA ,  Naoki SHIMIZU ,  Seiji KATSUTA ,  Shinji OTANI

    发明人： Kota ZENZAI ,  Hisayoshi OMORI ,  Takashi KANAYAMA ,  Kiyoyasu SAKURADA ,  Naoki SHIMIZU ,  Seiji KATSUTA ,  Shinji OTANI

    IPC分类号： H01G4/12 ,  H01G4/00

    CPC分类号： H01G4/30 ,  H01G4/005 ,  H01G4/012 ,  H01G4/12 ,  H01G4/248 ,  H01G4/252 ,  H01G13/006 ,  H05K3/1283 ,  H05K3/4664

    摘要： A ceramic body includes an inner electrode disposed inside the ceramic body and in which an end portion of the inner electrode extends to a surface of the ceramic body. An electrode layer is formed on the surface of the ceramic body so as to cover the end portion of the inner electrode, the electrode layer including a resin, a first metal filler that contains a first metal component, and a second metal filler that contains a second metal component having a higher melting point than the first metal component. A step of heating the electrode layer is performed to form an electrode including a metal layer that is located on the surface of the ceramic body and that includes the first and second metal components and a metal contained in the inner electrode.

    摘要翻译： 陶瓷体包括设置在陶瓷体内部的内部电极，内部电极的端部延伸到陶瓷体的表面。 在陶瓷体的表面上形成电极层，以覆盖内部电极的端部，包括树脂的电极层，含有第一金属成分的第一金属填料和含有第一金属成分的第二金属填料 具有比第一金属成分高的熔点的第二金属成分。 进行加热电极层的步骤，以形成包括位于陶瓷体表面上并且包括第一和第二金属成分的金属层的电极和内部电极中所含的金属。

    MEMORY DEVICE
    4.
    发明申请
    MEMORY DEVICE 审中-公开
    内存设备

    公开(公告)号：US20160266804A1

    公开(公告)日：2016-09-15

    申请号：US14852398

    申请日：2015-09-11

    申请人： Naoki SHIMIZU

    发明人： Naoki SHIMIZU

    IPC分类号： G06F3/06

    CPC分类号： G11C11/1673 ,  G06F13/161 ,  G11C11/1693 ,  G11C13/004 ,  G11C13/0061

    摘要： According to one embodiment, a memory device includes a memory area; and a control circuit, in response to a first command, configured to read out data from the memory area without outputting the data to a data line, subsequently, in response to a second command, configured to output the data to the data line, if the first command is not received after receiving an active command, in response to the second command, configured to output the data read out from the memory area to the data line.

    摘要翻译： 根据一个实施例，存储器装置包括存储区域; 以及控制电路，响应于第一命令，被配置为从存储器区域读出数据而不将数据输出到数据线，随后响应于第二命令将数据输出到数据线，如果 在接收到有效命令之后，响应于第二命令，第一命令被配置为将从存储器区域读出的数据输出到数据线。

    SEMICONDUCTOR MEMORY, MEMORY SYSTEM AND METHOD OF CONTROLLING SEMICONDUCTOR MEMORY
    5.
    发明申请
    SEMICONDUCTOR MEMORY, MEMORY SYSTEM AND METHOD OF CONTROLLING SEMICONDUCTOR MEMORY 有权
    半导体存储器，存储器系统和控制半导体存储器的方法

    公开(公告)号：US20160064061A1

    公开(公告)日：2016-03-03

    申请号：US14644152

    申请日：2015-03-10

    申请人： Naoki SHIMIZU

    发明人： Naoki SHIMIZU

    IPC分类号： G11C11/16 ,  G11C29/52 ,  G11C29/08

    CPC分类号： G11C11/1677 ,  G11C7/08 ,  G11C7/12 ,  G11C7/22 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1675 ,  G11C11/1693 ,  G11C29/52 ,  G11C2029/0411

    摘要： According to one embodiment, a semiconductor memory includes a memory area; an error detection circuit which detect an error of first data output from the memory area; and a control circuit which control the memory area and the error detection circuit. When the error is detected in the first data, the control circuit starts precharge of a bit line at a timing when a first period has elapsed from a start of a first operation of the memory area for output of the first data. When the error is not detected in the first data, the control circuit starts the precharge at a timing when a second period has elapsed from the start of the first operation, the second period is shorter than the first period.

    摘要翻译： 根据一个实施例，半导体存储器包括存储区域; 检测从存储区域输出的第一数据的错误的错误检测电路; 以及控制电路，其控制存储区域和误差检测电路。 当在第一数据中检测到错误时，控制电路在从用于输出第一数据的存储区域的第一操作开始经过第一周期的定时开始对位线进行预充电。 当在第一数据中未检测到错误时，控制电路在从第一操作开始经过第二周期的时刻开始预充电，第二周期比第一周期短。

    MULTILAYER CERAMIC ELECTRONIC COMPONENT
    6.
    发明申请
    MULTILAYER CERAMIC ELECTRONIC COMPONENT 有权
    多层陶瓷电子元件

    公开(公告)号：US20100220426A1

    公开(公告)日：2010-09-02

    申请号：US12784553

    申请日：2010-05-21

    申请人： Naoki SHIMIZU

    发明人： Naoki SHIMIZU

    IPC分类号： H01G4/228 ,  H01C7/18

    CPC分类号： H01G4/30 ,  H01G4/012 ,  H01G4/12

    摘要： A multilayer ceramic capacitor includes first internal electrodes extending to a first end surface of a ceramic element assembly, a plurality of second internal electrodes extending to a second end surface, floating internal electrodes arranged so as to overlap the first and second internal electrodes with ceramic layers disposed therebetween to define first and second effective regions, inner conductors that are elongated from the first end surface beyond a region that overlaps the first effective region in the direction of layering, and a relationship X1

    摘要翻译： 多层陶瓷电容器包括延伸到陶瓷元件组件的第一端面的第一内部电极，延伸到第二端面的多个第二内部电极，布置成与第一和第二内部电极重叠的陶瓷层的浮动内部电极 设置在它们之间以限定第一和第二有效区域，内部导体从第一端面延伸超过在分层方向上与第一有效区域重叠的区域，并且满足X1

    DESTINATION PREDICTION APPARATUS
    7.
    发明申请
    DESTINATION PREDICTION APPARATUS 有权
    目标预测装置

    公开(公告)号：US20150345970A1

    公开(公告)日：2015-12-03

    申请号：US14760898

    申请日：2013-01-21

    申请人： Kouhei TANAKA ,  Masaya AKIHARA ,  Mitsuo SHIMOTANI ,  Naoki SHIMIZU ,  Toshio KAWAGISHI

    发明人： Kouhei TANAKA ,  Masaya AKIHARA ,  Mitsuo SHIMOTANI ,  Toshio KAWAGISHI ,  Naoki SHIMIZU

    IPC分类号： G01C21/34 ,  G01C21/36

    CPC分类号： G01C21/3484 ,  G01C21/36 ,  G01C21/3617

    摘要： It is an object of the present invention to predict a destination easily, and a destination display method for displaying a predicted destination. The destination prediction apparatus of the present invention includes: a behavior history acquiring unit that acquires, the behavior history; a visit history acquiring unit that acquires the visit history; a similar behavior date-and-time extractor that performs a similarity determination between a behavior within a predetermined period prior to a present date and time and a behavior in another period with reference to the behavior history and that extracts a date and time of the behavior in another period determined to be similar as a similar behavior date and time from the behavior history; and a destination candidate extractor that extracts, as a destination candidate, a location visited within a predetermined period before or after the similar behavior date and time from the visit history.

    摘要翻译： 本发明的目的是容易地预测目的地，以及用于显示预测目的地的目的地显示方法。 本发明的目的地预测装置包括：行为历史获取单元，其获取行为历史; 获取访问历史的访问历史获取单元; 类似的行为日期和时间提取器，其执行在当前日期和时间之前的预定时间段内的行为与参考行为历史的另一时段中的行为之间的相似性确定，并提取行为的日期和时间 在另一个时期被确定为与行为历史相似的行为日期和时间; 以及目的地候选提取器，其从访问历史中提取在相似行为日期和时间之前或之后的预定时段内作为目的地候选者访问的位置。

    TRANSFER APPARATUS
    8.
    发明申请
    TRANSFER APPARATUS 审中-公开
    传送装置

    公开(公告)号：US20150336396A1

    公开(公告)日：2015-11-26

    申请号：US14719679

    申请日：2015-05-22

    申请人： Yuichi AIHARA ,  Naoki SHIMIZU

    发明人： Yuichi AIHARA ,  Naoki SHIMIZU

    IPC分类号： B41J2/325

    CPC分类号： B41J2/325 ,  B41J11/0005 ,  B65H15/00 ,  B65H29/125 ,  B65H29/70 ,  B65H2301/132 ,  B65H2301/51212 ,  B65H2301/51256 ,  B65H2403/512 ,  B65H2404/1421 ,  B65H2511/222 ,  B65H2511/413 ,  B65H2511/416 ,  B65H2513/11 ,  B65H2513/53 ,  B65H2515/40 ,  B65H2515/83 ,  B65H2701/1914 ,  B65H2220/02 ,  B65H2220/11 ,  B65H2220/01

    摘要： To provide a transfer apparatus correcting a curl of a card efficiently while preventing the card from deteriorating, a printing apparatus includes a transfer section transferring a transfer surface of a transfer film to the card, a rotating unit reversing the front side and back side of the card in two-sided transfer, a decurl mechanism correcting a curl of the card with the transfer surface transferred in the transfer section, and a control section controlling the decurl mechanism. The control section controls the decurl mechanism such that a correction amount for the card with the transfer surface transferred to one surface in two-sided transfer is smaller than a correction amount for the card in one-sided transfer, and that the total sum of correction amounts for respective surfaces of the card in two-sided transfer is smaller than the correction amount for the card in one-sided transfer.

    摘要翻译： 为了提供一种在防止卡劣化的同时有效地校正卡的卷曲的传送装置，打印装置包括将转印膜的转印面传送到卡的转印部，使转印膜的正面和背面反转的旋转单元 卡片以双面传送方式，一个去卷缩机构，用于校正传送在传送部分中的传送表面的卡片的卷曲;以及控制部分，控制分解机构。 控制部分控制分解机构，使得在双面传送中传送到一个表面的传送表面的卡的校正量小于单面传送中的卡的校正量，并且校正总和 卡片在双面传送中的各个表面的量小于单面传送中的卡的校正量。

    SEMICONDUCTOR MEMORY DEVICE
    9.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 审中-公开
    半导体存储器件

    公开(公告)号：US20150262631A1

    公开(公告)日：2015-09-17

    申请号：US14482925

    申请日：2014-09-10

    申请人： Naoki SHIMIZU

    发明人： Naoki SHIMIZU

    IPC分类号： G11C7/10 ,  G11C5/06 ,  G11C14/00

    CPC分类号： G11C7/1072 ,  G11C7/1018 ,  G11C7/1045 ,  G11C7/20 ,  G11C11/1675 ,  G11C11/1693 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2207/229 ,  G11C2213/79 ,  G11C2213/82

    摘要： According to one embodiment, there is provided a semiconductor memory device comprising: a memory cell array including a plurality of memory cells configured to be able to store data; a control circuit configured to control a write operation of data in the memory cell array, and an initialization operation of the memory cell array; and a register control circuit configured to receive a first command including second information for selecting first information relating to control of a cycle of a clock from completion of the write operation of data in the memory cell array to initialization of the memory cell array.

    摘要翻译： 根据一个实施例，提供了一种半导体存储器件，包括：存储单元阵列，包括被配置为能够存储数据的多个存储器单元; 控制电路，被配置为控制存储单元阵列中的数据的写入操作，以及存储单元阵列的初始化操作; 以及寄存器控制电路，被配置为接收包括第二信息的第一命令，所述第二信息用于从完成存储单元阵列中的数据的写入操作到存储器单元阵列的初始化，选择与时钟周期的控制有关的第一信息。

    SEMICONDUCTOR MEMORY DEVICE
    10.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 有权
    半导体存储器件

    公开(公告)号：US20150063015A1

    公开(公告)日：2015-03-05

    申请号：US14201618

    申请日：2014-03-07

    申请人： Naoki SHIMIZU

    发明人： Naoki SHIMIZU

    IPC分类号： G11C11/16

    CPC分类号： G11C11/1653 ,  G11C7/1093 ,  G11C8/10 ,  G11C11/1675 ,  G11C11/1693 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/0061 ,  G11C13/0069

    摘要： A semiconductor memory device includes: banks each including a memory cell array; word lines connected to rows of each of the banks; an address latch circuit configured to latch a full address for specifying one of the word lines, the full address including a first address and a second address; and a control circuit configured to ignore a reset operation for the first address as a target of a set operation, and overwrite the first address in accordance with the set operation when receiving a first command for specifying a reset operation for a bank and a set operation for the first address.

    摘要翻译： 半导体存储器件包括：各自包括存储单元阵列的存储体; 连接到每个银行的行的字线; 地址锁存电路，被配置为锁存用于指定字线之一的完整地址，所述完整地址包括第一地址和第二地址; 以及控制电路，被配置为忽略作为设置操作的目标的第一地址的复位操作，并且当接收到用于指定用于组的复位操作的第一命令和设置操作时，根据设置操作重写第一地址 为第一个地址。