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1.发明授权公开(公告)号：US08063487B2
公开(公告)日：2011-11-22
申请号：US12335673
申请日：2008-12-16
IPC分类号： H01L23/48
CPC分类号： H01L23/525 , H01L24/06 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/17 , H01L24/81 , H01L24/94 , H01L25/0657 , H01L25/18 , H01L2224/0401 , H01L2224/05548 , H01L2224/13027 , H01L2224/13099 , H01L2224/131 , H01L2224/1403 , H01L2224/14051 , H01L2225/06513 , H01L2225/06527 , H01L2225/06568 , H01L2924/0001 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/30105
摘要： A first conducting layer is formed on a side of a main surface on which an electrode terminal of a semiconductor device is provided in a semiconductor substrate. The first conducting layer is electrically connected to the electrode terminal of the semiconductor device. A mask layer that has an opening at a predetermined position is formed on the first conducting layer. A second conducting layer is formed inside the opening of the mask layer. The mask layer is removed. A relocation wiring that includes the first conducting layer and electrically draws out the electrode terminal is formed by performing anisotropic etching for the first conducting layer using the second conducting layer as a mask. Finally, a bump is formed on the relocation wiring by causing the second conducting layer to reflow.
摘要翻译： 第一导电层形成在半导体衬底中设置半导体器件的电极端子的主表面的一侧。 第一导电层电连接到半导体器件的电极端子。 在第一导电层上形成有在预定位置具有开口的掩模层。 在掩模层的开口内形成第二导电层。 去除掩模层。 通过使用第二导电层作为掩模对第一导电层进行各向异性蚀刻，形成包括第一导电层并电拔出电极端子的重定位布线。 最后，通过使第二导电层回流而在位移配线上形成凸点。
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2.发明申请公开(公告)号：US20120028463A1
公开(公告)日：2012-02-02
申请号：US13267048
申请日：2011-10-06
IPC分类号： H01L21/768
CPC分类号： H01L23/525 , H01L24/06 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/17 , H01L24/81 , H01L24/94 , H01L25/0657 , H01L25/18 , H01L2224/0401 , H01L2224/05548 , H01L2224/13027 , H01L2224/13099 , H01L2224/131 , H01L2224/1403 , H01L2224/14051 , H01L2225/06513 , H01L2225/06527 , H01L2225/06568 , H01L2924/0001 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/30105
摘要： A first conducting layer is formed on a side of a main surface on which an electrode terminal of a semiconductor device is provided in a semiconductor substrate. The first conducting layer is electrically connected to the electrode terminal of the semiconductor device. A mask layer that has an opening at a predetermined position is formed on the first conducting layer. A second conducting layer is formed inside the opening of the mask layer. The mask layer is removed. A relocation wiring that includes the first conducting layer and electrically draws out the electrode terminal is formed by performing anisotropic etching for the first conducting layer using the second conducting layer as a mask. Finally, a bump is formed on the relocation wiring by causing the second conducting layer to reflow.
摘要翻译： 第一导电层形成在半导体衬底中设置半导体器件的电极端子的主表面的一侧。 第一导电层电连接到半导体器件的电极端子。 在第一导电层上形成有在预定位置具有开口的掩模层。 在掩模层的开口内形成第二导电层。 去除掩模层。 通过使用第二导电层作为掩模对第一导电层进行各向异性蚀刻，形成包括第一导电层并电拔出电极端子的重定位布线。 最后，通过使第二导电层回流而在位移配线上形成凸点。
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3.发明授权公开(公告)号：US08569181B2
公开(公告)日：2013-10-29
申请号：US13267048
申请日：2011-10-06
IPC分类号： H01L21/461 , H01L21/38
CPC分类号： H01L23/525 , H01L24/06 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/17 , H01L24/81 , H01L24/94 , H01L25/0657 , H01L25/18 , H01L2224/0401 , H01L2224/05548 , H01L2224/13027 , H01L2224/13099 , H01L2224/131 , H01L2224/1403 , H01L2224/14051 , H01L2225/06513 , H01L2225/06527 , H01L2225/06568 , H01L2924/0001 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/30105
摘要： A first conducting layer is formed on a side of a main surface on which an electrode terminal of a semiconductor device is provided in a semiconductor substrate. The first conducting layer is electrically connected to the electrode terminal of the semiconductor device. A mask layer that has an opening at a predetermined position is formed on the first conducting layer. A second conducting layer is formed inside the opening of the mask layer. The mask layer is removed. A relocation wiring that includes the first conducting layer and electrically draws out the electrode terminal is formed by performing anisotropic etching for the first conducting layer using the second conducting layer as a mask. Finally, a bump is formed on the relocation wiring by causing the second conducting layer to reflow.
摘要翻译： 第一导电层形成在半导体衬底中设置半导体器件的电极端子的主表面的一侧。 第一导电层电连接到半导体器件的电极端子。 在第一导电层上形成有在预定位置具有开口的掩模层。 在掩模层的开口内形成第二导电层。 去除掩模层。 通过使用第二导电层作为掩模对第一导电层进行各向异性蚀刻，形成包括第一导电层并电拔出电极端子的重定位布线。 最后，通过使第二导电层回流而在位移配线上形成凸点。
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公开(公告)号：US08314491B2
公开(公告)日：2012-11-20
申请号：US12845937
申请日：2010-07-29
申请人： Soichi Yamashita , Tatsuo Migita , Tadashi Iijima , Masahiro Miyata , Masayuki Uchida , Takashi Togasaki , Hirokazu Ezawa
发明人： Soichi Yamashita , Tatsuo Migita , Tadashi Iijima , Masahiro Miyata , Masayuki Uchida , Takashi Togasaki , Hirokazu Ezawa
IPC分类号： H01L23/48
CPC分类号： H01L24/03 , H01L24/05 , H01L24/06 , H01L24/11 , H01L24/16 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/73 , H01L24/81 , H01L2224/02311 , H01L2224/02381 , H01L2224/0401 , H01L2224/04042 , H01L2224/05008 , H01L2224/05548 , H01L2224/05569 , H01L2224/05571 , H01L2224/05572 , H01L2224/05666 , H01L2224/0603 , H01L2224/06051 , H01L2224/11462 , H01L2224/1147 , H01L2224/11849 , H01L2224/13083 , H01L2224/13099 , H01L2224/13111 , H01L2224/13147 , H01L2224/13155 , H01L2224/16145 , H01L2224/2919 , H01L2224/32145 , H01L2224/45144 , H01L2224/48666 , H01L2224/73204 , H01L2224/73207 , H01L2224/73215 , H01L2224/81191 , H01L2924/00013 , H01L2924/00014 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01011 , H01L2924/01014 , H01L2924/01019 , H01L2924/01022 , H01L2924/01023 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/014 , H01L2924/14 , H01L2224/13599 , H01L2224/05599 , H01L2224/05099 , H01L2224/29099 , H01L2224/29599 , H01L2924/00 , H01L2224/05552 , H01L2224/45015 , H01L2924/207
摘要： According to one embodiment, a manufacturing method of a semiconductor device attained as follows. A dielectric layer having a first opening and a second opening reaching an electrode terminal is formed by modifying a photosensitive resin film on a substrate on which the electrode terminal of a first conductive layer is provided. Next, a second conductive layer that is electrically connected to the electrode terminal is formed on the dielectric layer that includes inside of the first opening, and a third conductive layer that has an oxidation-reduction potential of which difference from the oxidation-reduction potential of the first conductive layer is smaller than a difference of the oxidation-reduction potential between the first conductive layer and the second conductive layer is formed on the second conductive layer. Next, a dielectric layer having a third opening reaching the third conductive layer and a fourth opening reaching the electrode terminal via the second opening is formed by modifying a photosensitive resin film, and a bump that is electrically connected to the third conductive layer is formed.
摘要翻译： 根据一个实施例，半导体器件的制造方法如下。 通过改变在其上设置有第一导电层的电极端子的基板上的感光性树脂膜，形成具有第一开口和到达电极端子的第二开口的电介质层。 接下来，在包括第一开口的内部的电介质层上形成与电极端子电连接的第二导电层，以及具有与氧化还原电位不同的氧化还原电位的第三导电层 第一导电层小于在第二导电层上形成第一导电层和第二导电层之间的氧化还原电位的差异。 接下来，通过改变感光性树脂膜形成具有到达第三导电层的第三开口的电介质层和通过第二开口到达电极端子的第四开口，并且形成与第三导电层电连接的凸块。
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公开(公告)号：US20110024901A1
公开(公告)日：2011-02-03
申请号：US12845937
申请日：2010-07-29
申请人： Soichi Yamashita , Tatsuo Migita , Tadashi Iijima , Masahiro Miyata , Masayuki Uchida , Takashi Togasaki , Hirokazu Ezawa
发明人： Soichi Yamashita , Tatsuo Migita , Tadashi Iijima , Masahiro Miyata , Masayuki Uchida , Takashi Togasaki , Hirokazu Ezawa
IPC分类号： H01L23/52 , H01L21/283
CPC分类号： H01L24/03 , H01L24/05 , H01L24/06 , H01L24/11 , H01L24/16 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/73 , H01L24/81 , H01L2224/02311 , H01L2224/02381 , H01L2224/0401 , H01L2224/04042 , H01L2224/05008 , H01L2224/05548 , H01L2224/05569 , H01L2224/05571 , H01L2224/05572 , H01L2224/05666 , H01L2224/0603 , H01L2224/06051 , H01L2224/11462 , H01L2224/1147 , H01L2224/11849 , H01L2224/13083 , H01L2224/13099 , H01L2224/13111 , H01L2224/13147 , H01L2224/13155 , H01L2224/16145 , H01L2224/2919 , H01L2224/32145 , H01L2224/45144 , H01L2224/48666 , H01L2224/73204 , H01L2224/73207 , H01L2224/73215 , H01L2224/81191 , H01L2924/00013 , H01L2924/00014 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01011 , H01L2924/01014 , H01L2924/01019 , H01L2924/01022 , H01L2924/01023 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/014 , H01L2924/14 , H01L2224/13599 , H01L2224/05599 , H01L2224/05099 , H01L2224/29099 , H01L2224/29599 , H01L2924/00 , H01L2224/05552 , H01L2224/45015 , H01L2924/207
摘要： According to one embodiment, a manufacturing method of a semiconductor device attained as follows. A dielectric layer having a first opening and a second opening reaching an electrode terminal is formed by modifying a photosensitive resin film on a substrate on which the electrode terminal of a first conductive layer is provided. Next, a second conductive layer that is electrically connected to the electrode terminal is formed on the dielectric layer that includes inside of the first opening, and a third conductive layer that has an oxidation-reduction potential of which difference from the oxidation-reduction potential of the first conductive layer is smaller than a difference of the oxidation-reduction potential between the first conductive layer and the second conductive layer is formed on the second conductive layer. Next, a dielectric layer having a third opening reaching the third conductive layer and a fourth opening reaching the electrode terminal via the second opening is formed by modifying a photosensitive resin film, and a bump that is electrically connected to the third conductive layer is formed.
摘要翻译： 根据一个实施例，半导体器件的制造方法如下。 通过改变在其上设置有第一导电层的电极端子的基板上的感光性树脂膜，形成具有第一开口和到达电极端子的第二开口的电介质层。 接下来，在包括第一开口的内部的电介质层上形成与电极端子电连接的第二导电层，以及具有与氧化还原电位不同的氧化还原电位的第三导电层 第一导电层小于在第二导电层上形成第一导电层和第二导电层之间的氧化还原电位的差异。 接下来，通过改变感光性树脂膜形成具有到达第三导电层的第三开口的电介质层和通过第二开口到达电极端子的第四开口，并且形成与第三导电层电连接的凸块。
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6.发明申请公开(公告)号：US20090200664A1
公开(公告)日：2009-08-13
申请号：US12335673
申请日：2008-12-16
IPC分类号： H01L23/498 , H01L21/768
CPC分类号： H01L23/525 , H01L24/06 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/17 , H01L24/81 , H01L24/94 , H01L25/0657 , H01L25/18 , H01L2224/0401 , H01L2224/05548 , H01L2224/13027 , H01L2224/13099 , H01L2224/131 , H01L2224/1403 , H01L2224/14051 , H01L2225/06513 , H01L2225/06527 , H01L2225/06568 , H01L2924/0001 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/30105
摘要： A first conducting layer is formed on a side of a main surface on which an electrode terminal of a semiconductor device is provided in a semiconductor substrate. The first conducting layer is electrically connected to the electrode terminal of the semiconductor device. A mask layer that has an opening at a predetermined position is formed on the first conducting layer. A second conducting layer is formed inside the opening of the mask layer. The mask layer is removed. A relocation wiring that includes the first conducting layer and electrically draws out the electrode terminal is formed by performing anisotropic etching for the first conducting layer using the second conducting layer as a mask. Finally, a bump is formed on the relocation wiring by causing the second conducting layer to reflow.
摘要翻译： 第一导电层形成在半导体衬底中设置半导体器件的电极端子的主表面的一侧。 第一导电层电连接到半导体器件的电极端子。 在第一导电层上形成有在预定位置具有开口的掩模层。 在掩模层的开口内形成第二导电层。 去除掩模层。 通过使用第二导电层作为掩模对第一导电层进行各向异性蚀刻，形成包括第一导电层并电拔出电极端子的重定位布线。 最后，通过使第二导电层回流而在位移配线上形成凸点。
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公开(公告)号：US08703600B2
公开(公告)日：2014-04-22
申请号：US12721741
申请日：2010-03-11
CPC分类号： H01L24/11 , H01L24/73 , H01L25/0657 , H01L2224/05001 , H01L2224/05022 , H01L2224/05027 , H01L2224/05124 , H01L2224/05147 , H01L2224/05166 , H01L2224/05572 , H01L2224/05655 , H01L2224/13099 , H01L2224/1403 , H01L2224/16145 , H01L2224/32145 , H01L2224/32225 , H01L2224/45144 , H01L2224/45147 , H01L2224/48227 , H01L2224/48463 , H01L2224/73204 , H01L2224/73207 , H01L2224/73265 , H01L2225/0651 , H01L2225/06513 , H01L2225/06568 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/09701 , H01L2924/1306 , H01L2924/15311 , H01L2924/15787 , H01L2924/15788 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2924/00014
摘要： An electronic component in which an element is formed on a chip includes: a pad that is made of a conductive material and that is formed in a first bump formation region that is two-dimensionally arranged in center of one principle face and in a second bump formation region that is linearly arranged at peripheral border of the principle face; a passivation film that is formed on the principle face to cover portion except a formation position of the pad; a metal layer that is formed on the pad; and a bump that is made of a conductive material and that is formed on the metal layer by plating, wherein radius of the metal layer in the second bump formation region is smaller than radius of at least some of the metal layer in the first bump formation region.
摘要翻译： 其中元件形成在芯片上的电子部件包括：由导电材料制成并且形成在二维布置在一个原理面的中心的第一凸块形成区域中的衬垫和在第二凸起 在原理面的周边边缘线性排列的形成区域; 钝化膜，其形成在除了所述焊盘的形成位置之外的所述原理面上以覆盖部分; 形成在所述垫上的金属层; 以及由导电材料制成并且通过电镀在金属层上形成的凸块，其中第二凸块形成区域中的金属层的半径小于第一凸块形成中的至少一些金属层的半径 地区。
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公开(公告)号：US20100301472A1
公开(公告)日：2010-12-02
申请号：US12721741
申请日：2010-03-11
CPC分类号： H01L24/11 , H01L24/73 , H01L25/0657 , H01L2224/05001 , H01L2224/05022 , H01L2224/05027 , H01L2224/05124 , H01L2224/05147 , H01L2224/05166 , H01L2224/05572 , H01L2224/05655 , H01L2224/13099 , H01L2224/1403 , H01L2224/16145 , H01L2224/32145 , H01L2224/32225 , H01L2224/45144 , H01L2224/45147 , H01L2224/48227 , H01L2224/48463 , H01L2224/73204 , H01L2224/73207 , H01L2224/73265 , H01L2225/0651 , H01L2225/06513 , H01L2225/06568 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/09701 , H01L2924/1306 , H01L2924/15311 , H01L2924/15787 , H01L2924/15788 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2924/00014
摘要： An electronic component in which an element is formed on a chip includes: a pad that is made of a conductive material and that is formed in a first bump formation region that is two-dimensionally arranged in center of one principle face and in a second bump formation region that is linearly arranged at peripheral border of the principle face; a passivation film that is formed on the principle face to cover portion except a formation position of the pad; a metal layer that is formed on the pad; and a bump that is made of a conductive material and that is formed on the metal layer by plating, wherein radius of the metal layer in the second bump formation region is smaller than radius of at least some of the metal layer in the first bump formation region.
摘要翻译： 其中元件形成在芯片上的电子部件包括：由导电材料制成并且形成在二维布置在一个原理面的中心的第一凸块形成区域中的衬垫和在第二凸起 在原理面的周边边缘线性排列的形成区域; 钝化膜，其形成在除了所述焊盘的形成位置之外的所述原理面上以覆盖部分; 形成在所述垫上的金属层; 以及由导电材料制成并且通过电镀在金属层上形成的凸块，其中第二凸块形成区域中的金属层的半径小于第一凸块形成中的至少一些金属层的半径 地区。
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公开(公告)号：US08704367B2
公开(公告)日：2014-04-22
申请号：US13224787
申请日：2011-09-02
申请人： Tatsuo Migita , Hirokazu Ezawa , Soichi Yamashita , Koro Nagamine , Masahiro Miyata , Tatsuo Shiotsuki , Kiyoshi Muranishi
发明人： Tatsuo Migita , Hirokazu Ezawa , Soichi Yamashita , Koro Nagamine , Masahiro Miyata , Tatsuo Shiotsuki , Kiyoshi Muranishi
CPC分类号： H01L24/05 , H01L23/3192 , H01L24/03 , H01L24/11 , H01L24/13 , H01L24/81 , H01L2224/0231 , H01L2224/02311 , H01L2224/02313 , H01L2224/02331 , H01L2224/0235 , H01L2224/02381 , H01L2224/0239 , H01L2224/024 , H01L2224/0345 , H01L2224/03452 , H01L2224/0346 , H01L2224/03462 , H01L2224/0361 , H01L2224/03912 , H01L2224/0401 , H01L2224/05018 , H01L2224/05022 , H01L2224/05147 , H01L2224/05155 , H01L2224/05166 , H01L2224/05558 , H01L2224/05567 , H01L2224/05647 , H01L2224/05666 , H01L2224/05669 , H01L2224/05671 , H01L2224/05684 , H01L2224/11462 , H01L2224/1147 , H01L2224/11849 , H01L2224/119 , H01L2224/11901 , H01L2224/13076 , H01L2224/1308 , H01L2224/13083 , H01L2224/13111 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/818 , H01L2224/81801 , H01L2224/8185 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01024 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/01022 , H01L2924/04941 , H01L2924/01027 , H01L2924/01046 , H01L2924/01025 , H01L2924/0541 , H01L2224/05552 , H01L2924/00 , H01L2224/1146
摘要： According to one embodiment, a semiconductor substrate, a metal film, a surface modifying layer, and a redistribution trace are provided. On the semiconductor substrate, a wire and a pad electrode are formed. The metal film is formed over the semiconductor substrate. The surface modifying layer is formed on a surface layer of the metal film and improves the adhesion with a resist pattern. The redistribution trace is formed on the metal film via the surface modifying layer.
摘要翻译： 根据一个实施例，提供半导体衬底，金属膜，表面改性层和再分布迹线。 在半导体衬底上，形成导线和焊盘电极。 金属膜形成在半导体衬底上。 表面改性层形成在金属膜的表面层上，并提高了与抗蚀剂图案的粘合性。 通过表面改性层在金属膜上形成再分布迹线。
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公开(公告)号：US20120049356A1
公开(公告)日：2012-03-01
申请号：US13222332
申请日：2011-08-31
申请人： Tatsuo Migita , Hirokazu Ezawa , Soichi Yamashita , Masaya Shima
发明人： Tatsuo Migita , Hirokazu Ezawa , Soichi Yamashita , Masaya Shima
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L24/11 , H01L21/76885 , H01L23/293 , H01L23/3157 , H01L23/562 , H01L24/03 , H01L24/05 , H01L24/13 , H01L2224/02331 , H01L2224/0235 , H01L2224/0239 , H01L2224/03462 , H01L2224/0401 , H01L2224/05019 , H01L2224/05022 , H01L2224/05111 , H01L2224/05116 , H01L2224/05118 , H01L2224/05147 , H01L2224/05149 , H01L2224/05155 , H01L2224/05157 , H01L2224/05171 , H01L2224/05181 , H01L2224/05572 , H01L2224/05582 , H01L2224/05647 , H01L2224/05666 , H01L2224/05669 , H01L2224/05671 , H01L2224/05684 , H01L2224/11462 , H01L2224/1147 , H01L2224/11849 , H01L2224/13083 , H01L2224/13099 , H01L2224/13111 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/94 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01024 , H01L2924/01025 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2224/03 , H01L2224/11 , H01L2924/01028 , H01L2224/05552 , H01L2924/00
摘要： According to one embodiment, a semiconductor substrate, a redistribution trace, and a surface layer are provided. On the semiconductor substrate, a wire and a pad electrode are formed. The redistribution trace is formed on the semiconductor substrate. The surface layer is larger in width than the redistribution trace.
摘要翻译： 根据一个实施例，提供半导体衬底，再分布迹线和表面层。 在半导体衬底上，形成导线和焊盘电极。 再分布痕迹形成在半导体衬底上。 表面层的宽度大于再分布迹线。
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