公开(公告)号：US20160045948A1

公开(公告)日：2016-02-18

申请号：US14783210

申请日：2013-04-08

Applicant: Masatake SHIMIZU ,  Akira TAKASHIMA

Inventor： Masatake SHIMIZU ,  Akira TAKASHIMA

IPC: B21D53/14

CPC classification number: B21D53/14 ,  F16G1/20 ,  F16G5/16

Abstract: In order to restrain the length of an endless metal ring from dispersing, a method of manufacturing a CVT belt has a first-stage stretching step of extending a circumferential length of an endless metal belt by widening distances among rollers. The method includes a measuring step of measuring a spring-back amount of the endless metal belt in the first-stage stretching step. The method includes a calculating step of calculating a predicted spring-back amount that is predicted from the measured spring-back amount. The method also includes a second-stage stretching step of stretching the endless metal belt to process the endless metal belt into a predetermined circumferential length by further widening the distances among the rollers based on the predicted spring-back amount.

Abstract translation: 为了限制环形金属环的长度分散，制造CVT带的方法具有通过扩大辊之间的距离来延伸环形金属带的圆周长度的第一阶段拉伸步骤。 该方法包括在第一阶段拉伸步骤中测量环形金属带的回弹量的测量步骤。 该方法包括：计算步骤，根据测得的回弹量计算预测的弹回量。 该方法还包括第二阶段拉伸步骤，其通过基于预测的回弹量进一步加宽辊之间的距离来拉伸环形金属带以将环形金属带加工成预定的周长。

公开(公告)号：US20120243293A1

公开(公告)日：2012-09-27

申请号：US13234796

申请日：2011-09-16

Applicant: Akira TAKASHIMA ,  Reika Ichihara

Inventor： Akira TAKASHIMA ,  Reika Ichihara

IPC: G11C11/21

CPC classification number: G11C11/5685 ,  G11C13/0007 ,  G11C13/003 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/0092 ,  G11C2213/33 ,  G11C2213/76

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell includes a variable resistance element and a capacitor connected in series between first and second conductive lines, and a control circuit applying one of first and second voltage pulses to the memory cell. The capacitor is charged by a leading edge of one of the first and second voltage pulses, and discharged a trailing edge of one of the first and second voltage pulses. The control circuit makes waveforms of the trailing edges of the first and second voltage pulses be different, changes a resistance value of the variable resistance element from a first resistance value to a second resistance value by using the first voltage pulse, and changes the resistance value of the variable resistance element from the second resistance value to the first resistance value by using the second voltage pulse.

Abstract translation: 根据一个实施例，非易失性半导体存储器件包括存储单元，其包括可变电阻元件和串联连接在第一和第二导线之间的电容器，以及将第一和第二电压脉冲之一施加到存储单元的控制电路。 电容器由第一和第二电压脉冲之一的前沿充电，并且将第一和第二电压脉冲之一的后沿放电。 控制电路使得第一和第二电压脉冲的后沿的波形不同，通过使用第一电压脉冲将可变电阻元件的电阻值从第一电阻值改变为第二电阻值，并且改变电阻值 通过使用第二电压脉冲从第二电阻值到第一电阻值。

公开(公告)号：US20120025297A1

公开(公告)日：2012-02-02

申请号：US13204412

申请日：2011-08-05

Applicant: Akira TAKASHIMA ,  Masao SHINGU ,  Koichi MURAOKA

Inventor： Akira TAKASHIMA ,  Masao SHINGU ,  Koichi MURAOKA

IPC: H01L29/792 ,  H01L21/336

CPC classification number: H01L21/28282 ,  H01L21/02145 ,  H01L21/02156 ,  H01L21/02161 ,  H01L21/28273 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/4234 ,  H01L29/513

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a source region and a drain region provided on a surface area of a semiconductor region, a tunnel insulating film provided on a channel between the source region and the drain region, a charge storage layer provided on the tunnel insulating film, a first dielectric film provided on the charge storage layer and containing lanthanum aluminum silicon oxide or oxynitride, a second dielectric film provided on the first dielectric film and containing oxide or oxynitride containing at least one of hafnium (Hf), zirconium (Zr), titanium (Ti), and a rare earth metal, and a control gate electrode provided on the second dielectric film.

Abstract translation: 根据一个实施例，非易失性半导体存储器件包括设置在半导体区域的表面区域上的源极区域和漏极区域，设置在源极区域和漏极区域之间的沟道上的隧道绝缘膜，设置有电荷存储层 在隧道绝缘膜上，设置在电荷存储层上并含有镧铝氧化物或氧氮化物的第一电介质膜，设置在第一电介质膜上并含有氧化物或氮氧化物的第二电介质膜，其含有铪（Hf）， 锆（Zr），钛（Ti）和稀土金属，以及设置在第二电介质膜上的控制栅电极。

公开(公告)号：US20120243292A1

公开(公告)日：2012-09-27

申请号：US13234388

申请日：2011-09-16

Applicant: Akira TAKASHIMA ,  Daisuke Matsushita ,  Takashi Yamauchi ,  Yuuichi Kamimuta ,  Hidenori Miyagawa

Inventor： Akira TAKASHIMA ,  Daisuke Matsushita ,  Takashi Yamauchi ,  Yuuichi Kamimuta ,  Hidenori Miyagawa

IPC: G11C11/00 ,  H01L21/8239 ,  H01L45/00

CPC classification number: H01L45/04 ,  G11C11/56 ,  G11C13/0002 ,  G11C13/0007 ,  G11C2213/33 ,  G11C2213/52 ,  H01L27/101 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/085 ,  H01L45/148

Abstract: According to one embodiment, a memory device includes a first electrode including a crystallized SixGe1-x layer (0≦x

Abstract translation: 根据一个实施例，存储器件包括包括结晶的SixGe1-x层（0和n1E; x <1）的第一电极，包括金属元件的第二电极，在第一和第二电极之间的可变电阻部分， 非晶Si层，以及控制非晶Si层中的细丝的控制电路，所述灯丝包括金属元件。

公开(公告)号：US20100065886A1

公开(公告)日：2010-03-18

申请号：US12482054

申请日：2009-06-10

Applicant: Yoshiki KAMATA ,  Akira TAKASHIMA

Inventor： Yoshiki KAMATA ,  Akira TAKASHIMA

IPC: H01L29/78 ,  H01L21/335

CPC classification number: H01L29/24 ,  H01L21/02381 ,  H01L21/02521 ,  H01L21/02532 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/2658 ,  H01L29/1054 ,  H01L29/517 ,  H01L29/785

Abstract: According to an aspect of the present invention, there is provided a semiconductor device including: a substrate that includes a semiconductor region including Ge as a primary component; a compound layer that is formed above the semiconductor region, that includes Ge and that has a non-metallic characteristic; an insulator film that is formed above the compound layer; an electrode that is formed above the insulator film; and source/drain regions that is formed in the substrate so as to sandwich the electrode therebetween.

Abstract translation: 根据本发明的一个方面，提供了一种半导体器件，包括：衬底，其包括以Ge为主要成分的半导体区域; 形成在半导体区域上方的包含Ge并且具有非金属特性的化合物层; 形成在化合物层上方的绝缘膜; 形成在绝缘膜上的电极; 以及形成在基板中以将电极夹在其间的源极/漏极区域。

公开(公告)号：US20090107586A1

公开(公告)日：2009-04-30

申请号：US12051286

申请日：2008-03-19

Applicant: Akira TAKASHIMA ,  Koichi Muraoka

Inventor： Akira TAKASHIMA ,  Koichi Muraoka

IPC: C23C8/10

CPC classification number: C23C14/08 ,  C23C14/24 ,  C23C14/50 ,  C23C14/564 ,  H01L21/31604 ,  H01L21/31641 ,  H01L21/31645

Abstract: A method for manufacturing a lanthanum oxide compound on a substrate includes: setting the number of H2O molecule, the number of CO molecule and the number of CO2 molecule to one-half or less, one-fifth or less and one-tenth or less per one lanthanum atom, respectively, the H2O molecule, the CO molecule and the CO2 molecule being originated from an H2O gas component, a CO gas component and a CO2 gas component in an atmosphere under manufacture; and supplying a metal raw material containing at least one selected from the group consisting of lanthanum, aluminum, titanium, zirconium and hafnium and an oxygen raw material gas simultaneously for the substrate under the condition that the number of O2 molecule are set to 20 or more per one lanthanum atom, thereby manufacturing the lanthanum oxide compound on the substrate.

Abstract translation: 在基材上制造氧化镧化合物的方法包括：将H 2 O分子的数量，CO分子的数目和CO 2分子的数量设定为每分钟的一半以下，五分之一以下，十分之一以下 一个镧原子分别来自制造气氛中的H 2 O分子，CO分子和CO 2分子源自H 2 O气体组分，CO气体组分和CO 2气体组分; 在氧分子数为20以上的条件下，向基板供给含有选自镧，铝，钛，锆，铪和氧原料气体中的至少一种的金属原料 每一个镧原子，从而在基底上制造氧化镧化合物。

公开(公告)号：US20090057750A1

公开(公告)日：2009-03-05

申请号：US12049875

申请日：2008-03-17

Applicant: Akira TAKASHIMA ,  Shoko Kikuchi ,  Koichi Muraoka

Inventor： Akira TAKASHIMA ,  Shoko Kikuchi ,  Koichi Muraoka

IPC: H01L29/00

CPC classification number: H01L29/7881 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/517 ,  H01L29/792

Abstract: A nonvolatile semiconductor memory element includes a semiconductor substrate, a source region and a drain region which are provided separately in the semiconductor substrate, a tunnel insulating layer which is provided between the source region and the drain region on the semiconductor substrate, a charge storage layer which is provided on the tunnel insulating layer, a block insulating layer which is provided on the charge storage layer and includes a crystallized lanthanum aluminate layer, and a control gate electrode which is provided on the block insulating layer.

Abstract translation: 非易失性半导体存储元件包括分别设置在半导体衬底中的半导体衬底，源极区域和漏极区域，设置在半导体衬底上的源极区域和漏极区域之间的隧道绝缘层，电荷存储层 其设置在隧道绝缘层上，块状绝缘层设置在电荷存储层上，并且包含结晶的铝酸镧层，以及设置在块绝缘层上的控制栅电极。

公开(公告)号：US20080211011A1

公开(公告)日：2008-09-04

申请号：US12024297

申请日：2008-02-01

Applicant: Akira TAKASHIMA ,  Kouichi Muraoka

Inventor： Akira TAKASHIMA ,  Kouichi Muraoka

IPC: H01L29/792

CPC classification number: H01L29/792 ,  H01L29/685

Abstract: It is made possible to provide a nonvolatile semiconductor memory element that can be miniaturized and can store multi-level data. A nonvolatile semiconductor memory element includes a semiconductor substrate; a source region and a drain region formed at a distance from each other in the semiconductor substrate; and a gate structure formed on a portion of the semiconductor substrate, the portion being located between the source region and the drain region. The gate structure includes a tunnel insulating layer, a resistance variable layer formed above the tunnel insulating layer and made of a metal oxide, and a first electrode formed on the resistance variable layer.

Abstract translation: 可以提供可以小型化并且可以存储多级数据的非易失性半导体存储元件。 非易失性半导体存储元件包括半导体衬底; 在半导体衬底中形成为彼此间隔一定距离的源极区域和漏极区域; 以及形成在半导体衬底的一部分上的栅极结构，该部分位于源极区和漏极区之间。 栅极结构包括隧道绝缘层，形成在隧道绝缘层上方并由金属氧化物构成的电阻变化层，以及形成在电阻变化层上的第一电极。

公开(公告)号：US20110092065A1

公开(公告)日：2011-04-21

申请号：US12976089

申请日：2010-12-22

Applicant: Eiji YOSHIDA ,  Takao OHNO ,  Yoshito AKUTAGAWA ,  Koji SAWAHATA ,  Masataka MIZUKOSHI ,  Takao NISHIMURA ,  Akira TAKASHIMA ,  Mitsuhisa WATANABE

Inventor： Eiji YOSHIDA ,  Takao OHNO ,  Yoshito AKUTAGAWA ,  Koji SAWAHATA ,  Masataka MIZUKOSHI ,  Takao NISHIMURA ,  Akira TAKASHIMA ,  Mitsuhisa WATANABE

IPC: H01L21/44

CPC classification number: H01L21/76898 ,  H01L23/3128 ,  H01L23/481 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/02371 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/06181 ,  H01L2224/13008 ,  H01L2224/13009 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/45144 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06551 ,  H01L2225/06555 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01047 ,  H01L2924/0106 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/05552 ,  H01L2924/00

Abstract: A semiconductor device is provided that forms a three-dimensional semiconductor device having semiconductor devices stacked on one another. In this semiconductor device, a hole is formed in a silicon semiconductor substrate that has an integrated circuit unit and an electrode pad formed on a principal surface on the outer side. The hole is formed by etching, with the electrode pad serving as an etching stopper layer. An embedded electrode is formed in the hole. This embedded electrode serves to electrically lead the electrode pad to the principal surface on the bottom side of the silicon semiconductor substrate.

Abstract translation: 提供一种半导体器件，其形成具有彼此堆叠的半导体器件的三维半导体器件。 在该半导体器件中，在具有形成在外侧的主面上的集成电路单元和电极焊盘的硅半导体基板中形成有孔。 通过蚀刻形成孔，电极焊盘用作蚀刻停止层。 埋入电极形成在孔中。 该嵌入电极用于将电极焊盘导电到硅半导体衬底的底侧的主表面。

公开(公告)号：US20090057751A1

公开(公告)日：2009-03-05

申请号：US12199036

申请日：2008-08-27

Applicant: Keiko ARIYOSHI ,  Akira TAKASHIMA ,  Shoko KIKUCHI ,  Koichi MURAOKA

Inventor： Keiko ARIYOSHI ,  Akira TAKASHIMA ,  Shoko KIKUCHI ,  Koichi MURAOKA

IPC: H01L29/788 ,  H01L29/792

CPC classification number: H01L29/7881 ,  H01L21/28273 ,  H01L21/28282 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/513 ,  H01L29/517

Abstract: A nonvolatile semiconductor memory device according to an example of the present invention includes a semiconductor region, source/drain areas arranged separately in the semiconductor region, a tunnel insulating film arranged on a channel region between the source/drain areas, a floating gate electrode arranged on the tunnel insulating film, an inter-electrode insulating film arranged on the floating gate electrode, and a control gate electrode arranged on the inter-electrode insulating film. The inter-electrode insulating film includes La, Al and Si.

Abstract translation: 根据本发明实施例的非易失性半导体存储器件包括半导体区域，在半导体区域中单独布置的源极/漏极区域，布置在源极/漏极区域之间的沟道区域上的隧道绝缘膜，布置成 在隧道绝缘膜上，布置在浮栅电极上的电极间绝缘膜和布置在电极间绝缘膜上的控制栅电极。 电极间绝缘膜包括La，Al和Si。