公开(公告)号：US20110092065A1

公开(公告)日：2011-04-21

申请号：US12976089

申请日：2010-12-22

Applicant: Eiji YOSHIDA ,  Takao OHNO ,  Yoshito AKUTAGAWA ,  Koji SAWAHATA ,  Masataka MIZUKOSHI ,  Takao NISHIMURA ,  Akira TAKASHIMA ,  Mitsuhisa WATANABE

Inventor： Eiji YOSHIDA ,  Takao OHNO ,  Yoshito AKUTAGAWA ,  Koji SAWAHATA ,  Masataka MIZUKOSHI ,  Takao NISHIMURA ,  Akira TAKASHIMA ,  Mitsuhisa WATANABE

IPC: H01L21/44

CPC classification number: H01L21/76898 ,  H01L23/3128 ,  H01L23/481 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/02371 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/06181 ,  H01L2224/13008 ,  H01L2224/13009 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/45144 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06551 ,  H01L2225/06555 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01047 ,  H01L2924/0106 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/05552 ,  H01L2924/00

Abstract: A semiconductor device is provided that forms a three-dimensional semiconductor device having semiconductor devices stacked on one another. In this semiconductor device, a hole is formed in a silicon semiconductor substrate that has an integrated circuit unit and an electrode pad formed on a principal surface on the outer side. The hole is formed by etching, with the electrode pad serving as an etching stopper layer. An embedded electrode is formed in the hole. This embedded electrode serves to electrically lead the electrode pad to the principal surface on the bottom side of the silicon semiconductor substrate.

Abstract translation: 提供一种半导体器件，其形成具有彼此堆叠的半导体器件的三维半导体器件。 在该半导体器件中，在具有形成在外侧的主面上的集成电路单元和电极焊盘的硅半导体基板中形成有孔。 通过蚀刻形成孔，电极焊盘用作蚀刻停止层。 埋入电极形成在孔中。 该嵌入电极用于将电极焊盘导电到硅半导体衬底的底侧的主表面。

公开(公告)号：US07812439B2

公开(公告)日：2010-10-12

申请号：US12169072

申请日：2008-07-08

Applicant: Mitsuhisa Watanabe ,  Ichiro Anjo

Inventor： Mitsuhisa Watanabe ,  Ichiro Anjo

IPC: H01L23/04

CPC classification number: H01L21/6836 ,  H01L21/563 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/06 ,  H01L24/81 ,  H01L24/83 ,  H01L24/86 ,  H01L24/90 ,  H01L24/97 ,  H01L2221/68327 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/06136 ,  H01L2224/1134 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/75743 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/83191 ,  H01L2224/83194 ,  H01L2224/838 ,  H01L2224/83851 ,  H01L2224/97 ,  H01L2924/00013 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/181 ,  H01L2224/81 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A semiconductor apparatus includes a semiconductor chip, a wired board, a plurality of bump electrodes, a plurality of external terminals, and insulating material. The semiconductor chip includes a plurality of electrode pads arranged in a central area on one surface. The wired board is arranged as facing one surface of the semiconductor chip, and includes a wiring. The bump electrode is provided between surfaces at which the semiconductor chip and the wired board face each other, and electrically connects the electrode pad and the wiring. The external terminal corresponds to a plurality of bump electrodes, and is mounted on the wired board. The insulating material is provided between the semiconductor chip and the wired board, and covers at least a connection part between the bump electrode and the wiring. The wiring of the wired board is configured to run in a straight line from a bump electrode-mounted position in a semiconductor chip-mounted surface of the wired board, to an external terminal-mounted surface of the wired board, and also, electrically connect the bump electrode and the corresponding external terminal.

Abstract translation: 半导体装置包括半导体芯片，布线板，多个凸块电极，多个外部端子和绝缘材料。 半导体芯片包括布置在一个表面上的中心区域中的多个电极焊盘。 布线板被布置为面对半导体芯片的一个表面，并且包括布线。 凸起电极设置在半导体芯片和布线板彼此面对的表面之间，并且电连接电极焊盘和布线。 外部端子对应于多个凸起电极，并且安装在布线板上。 绝缘材料设置在半导体芯片和布线板之间，并且至少覆盖凸起电极和布线之间的连接部分。 布线基板的布线被配置为从布线板的半导体芯片安装表面中的突起电极安装位置到布线板的外部端子安装表面的直线运行，并且还电连接 凸起电极和相应的外部端子。

公开(公告)号：US20090020873A1

公开(公告)日：2009-01-22

申请号：US12173245

申请日：2008-07-15

Applicant: Mitsuhisa Watanabe ,  Ichiro Anjoh

Inventor： Mitsuhisa Watanabe ,  Ichiro Anjoh

IPC: H01L23/48 ,  H01L21/56

CPC classification number: H01L21/561 ,  H01L21/6835 ,  H01L21/6836 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/544 ,  H01L24/06 ,  H01L24/16 ,  H01L24/17 ,  H01L24/27 ,  H01L24/90 ,  H01L24/94 ,  H01L2221/68327 ,  H01L2221/68381 ,  H01L2223/54486 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/06136 ,  H01L2224/1134 ,  H01L2224/13099 ,  H01L2224/1601 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/274 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/75 ,  H01L2224/81193 ,  H01L2224/83191 ,  H01L2224/83194 ,  H01L2224/83856 ,  H01L2224/90 ,  H01L2924/00013 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01068 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/3025 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2924/3512 ,  H01L2924/00

Abstract: A semiconductor apparatus includes a semiconductor chip in which a plurality of electrode pads are provided on a main surface, and a plurality of bump electrodes are provided on the electrode pads of the semiconductor chip. The semiconductor apparatus also includes a wired board which is allocated in a side of the main surface of the semiconductor chip, and is positioned in a central area of the main surface of the semiconductor chip so as to be separated from an edge part of the semiconductor chip by at least 50 μm or more. The semiconductor apparatus also includes a plurality of external terminals which are provided on the wired board, and which are electrically connected to a plurality of bump electrodes through wirings of the wired board, and sealing part which is provided between the semiconductor chip and the wired board, is made of underfill material that covers a connection part between the bump electrode and the wiring.

Abstract translation: 半导体装置包括半导体芯片，其中多个电极焊盘设置在主表面上，并且多个凸起电极设置在半导体芯片的电极焊盘上。 半导体装置还包括布线基板，其分配在半导体芯片的主表面的一侧，并且位于半导体芯片的主表面的中心区域中，以与半导体芯片的边缘部分分离 芯片至少有50个以上。 半导体装置还包括设置在布线板上的多个外部端子，并且通过布线板的布线与多个凸起电极电连接，以及设置在半导体芯片和布线板之间的密封部 由底部填充材料制成，其覆盖凸起电极和布线之间的连接部分。

公开(公告)号：US20050221589A1

公开(公告)日：2005-10-06

申请号：US11075758

申请日：2005-03-10

Applicant: Kazuo Teshirogi ,  Yuzo Shimobeppu ,  Kazuhiro Yoshimoto ,  Mitsuhisa Watanabe ,  Yoshiaki Shinjo ,  Eiji Yoshida ,  Noboru Hayasaka

Inventor： Kazuo Teshirogi ,  Yuzo Shimobeppu ,  Kazuhiro Yoshimoto ,  Mitsuhisa Watanabe ,  Yoshiaki Shinjo ,  Eiji Yoshida ,  Noboru Hayasaka

IPC: H01L21/68 ,  H01L21/00 ,  H01L21/301 ,  H01L21/304 ,  H01L21/52 ,  H01L21/58 ,  H01L21/60 ,  H01L21/683 ,  H01L21/687

CPC classification number: H01L21/67092 ,  B24B37/042 ,  B32B37/003 ,  B32B37/1018 ,  B32B38/0012 ,  B32B2310/0831 ,  B32B2457/14 ,  H01L21/304 ,  H01L21/67132 ,  H01L21/6836 ,  H01L21/6838 ,  H01L21/78 ,  H01L24/27 ,  H01L24/29 ,  H01L24/83 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/83191 ,  H01L2224/8385 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/07802 ,  Y10T29/5313 ,  Y10T29/53191 ,  Y10T428/1452 ,  H01L2924/3512 ,  H01L2924/00

Abstract: The present invention relates to a method of manufacturing a semiconductor substrate including the back grind step, the dicing step, the pick up step, and the die bonding step of the wafer; and to a semiconductor substrate jig used in such method. The object of the present invention is to mitigate the effect and to prevent damage caused by the lack of strength in thinned semiconductor substrates. A jig with an outer frame 21, and a rubber film 22 arranged within the outer frame 21 and having increasing and decreasing body size while deforming its shape by supplying air therein are provided. As the volume of the rubber film 22 increases, the wafer-fixing jig 20 deforms the rubber film and allows the tapes 2 and 6 arranged between the wafer 1 and the rubber film 22A to be pushed toward the wafer 1 gradually from the center outward. The attachment step, the back grind step, the tape reapplication step, the pick up step and the die bonding step are conducted using such wafer-fixing jig.

公开(公告)号：US20050167812A1

公开(公告)日：2005-08-04

申请号：US11062735

申请日：2005-02-23

Applicant: Eiji Yoshida ,  Takao Ohno ,  Yoshito Akutagawa ,  Koji Sawahata ,  Masataka Mizukoshi ,  Takao Nishimura ,  Akira Takashima ,  Mitsuhisa Watanabe

Inventor： Eiji Yoshida ,  Takao Ohno ,  Yoshito Akutagawa ,  Koji Sawahata ,  Masataka Mizukoshi ,  Takao Nishimura ,  Akira Takashima ,  Mitsuhisa Watanabe

IPC: H01L21/768 ,  H01L23/31 ,  H01L23/48 ,  H01L23/485 ,  H01L23/522 ,  H01L25/065 ,  H01L29/76

CPC classification number: H01L21/76898 ,  H01L23/3128 ,  H01L23/481 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/02371 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/06181 ,  H01L2224/13008 ,  H01L2224/13009 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/45144 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06551 ,  H01L2225/06555 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01047 ,  H01L2924/0106 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/05552 ,  H01L2924/00

Abstract: A semiconductor device is provided that forms a three-dimensional semiconductor device having semiconductor devices stacked on one another. In this semiconductor device, a hole is formed in a silicon semiconductor substrate that has an integrated circuit unit and an electrode pad formed on a principal surface on the outer side. The hole is formed by etching, with the electrode pad serving as an etching stopper layer. An embedded electrode is formed in the hole. This embedded electrode serves to electrically lead the electrode pad to the principal surface on the bottom side of the silicon semiconductor substrate.

Abstract translation: 提供一种半导体器件，其形成具有彼此堆叠的半导体器件的三维半导体器件。 在该半导体器件中，在具有形成在外侧的主面上的集成电路单元和电极焊盘的硅半导体基板中形成有孔。 通过蚀刻形成孔，电极焊盘用作蚀刻停止层。 埋入电极形成在孔中。 该嵌入电极用于将电极焊盘导电到硅半导体衬底的底侧的主表面。

公开(公告)号：US08810047B2

公开(公告)日：2014-08-19

申请号：US12588360

申请日：2009-10-13

Applicant: Mitsuhisa Watanabe ,  Fumitomo Watanabe

Inventor： Mitsuhisa Watanabe ,  Fumitomo Watanabe

IPC: H01L23/29

CPC classification number: H01L23/49816 ,  H01L21/561 ,  H01L21/565 ,  H01L21/6835 ,  H01L23/13 ,  H01L23/3128 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/85 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L2221/68331 ,  H01L2224/04042 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/48465 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/85201 ,  H01L2224/85205 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06572 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/07802 ,  H01L2924/15159 ,  H01L2924/15184 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/0401

Abstract: A semiconductor device includes: a substrate having first and second surfaces, the first surface comprising first and second regions; a first semiconductor chip covering the first region; a first seal covering the second region and the first semiconductor chip; and a second seal covering the second surface.

Abstract translation: 半导体器件包括：具有第一和第二表面的衬底，第一表面包括第一和第二区域; 覆盖所述第一区域的第一半导体芯片; 覆盖所述第二区域和所述第一半导体芯片的第一密封件; 以及覆盖所述第二表面的第二密封件。

公开(公告)号：US08441126B2

公开(公告)日：2013-05-14

申请号：US13106333

申请日：2011-05-12

Applicant: Mitsuhisa Watanabe ,  Ichiro Anjoh

Inventor： Mitsuhisa Watanabe ,  Ichiro Anjoh

IPC: H01L23/498

CPC classification number: H01L21/561 ,  H01L21/6835 ,  H01L21/6836 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/544 ,  H01L24/06 ,  H01L24/16 ,  H01L24/17 ,  H01L24/27 ,  H01L24/90 ,  H01L24/94 ,  H01L2221/68327 ,  H01L2221/68381 ,  H01L2223/54486 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/06136 ,  H01L2224/1134 ,  H01L2224/13099 ,  H01L2224/1601 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/274 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/75 ,  H01L2224/81193 ,  H01L2224/83191 ,  H01L2224/83194 ,  H01L2224/83856 ,  H01L2224/90 ,  H01L2924/00013 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01068 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/3025 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2924/3512 ,  H01L2924/00

Abstract: A semiconductor apparatus includes a semiconductor chip in which a plurality of electrode pads are provided on a main surface, and a plurality of bump electrodes are provided on the electrode pads of the semiconductor chip. The semiconductor apparatus also includes a wired board which is allocated in a side of the main surface of the semiconductor chip, and is positioned in a central area of the main surface of the semiconductor chip so as to be separated from an edge part of the semiconductor chip by at least 50 μm or more. The semiconductor apparatus also includes a plurality of external terminals which are provided on the wired board, and which are electrically connected to a plurality of bump electrodes through wirings of the wired board, and sealing part which is provided between the semiconductor chip and the wired board, is made of underfill material that covers a connection part between the bump electrode and the wiring.

Abstract translation: 半导体装置包括半导体芯片，其中多个电极焊盘设置在主表面上，并且多个凸起电极设置在半导体芯片的电极焊盘上。 半导体装置还包括布线基板，其分配在半导体芯片的主表面的一侧，并且位于半导体芯片的主表面的中心区域中，以与半导体芯片的边缘部分分离 芯片至少有50个以上。 半导体装置还包括设置在布线板上的多个外部端子，并且通过布线板的布线与多个凸起电极电连接，以及设置在半导体芯片和布线板之间的密封部 由底部填充材料制成，其覆盖凸起电极和布线之间的连接部分。

公开(公告)号：US08203222B2

公开(公告)日：2012-06-19

申请号：US12457896

申请日：2009-06-24

Applicant: Mitsuhisa Watanabe ,  Koichi Hatakeyama ,  Keiyo Kusanagi

Inventor： Mitsuhisa Watanabe ,  Koichi Hatakeyama ,  Keiyo Kusanagi

IPC: H01L23/29

CPC classification number: H01L23/3128 ,  H01L21/561 ,  H01L23/3135 ,  H01L23/562 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06589 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/07802 ,  H01L2924/15184 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device includes a substrate, a semiconductor chip, and first and second insulations. The substrate has at least a first region and a second region. The semiconductor chip structure covers the first region. The first insulation covers the second region. The first insulation has a first thermal expansion coefficient approximately equal to that of the semiconductor chip structure. The second insulation covers the semiconductor chip structure and the first insulation so that the semiconductor chip structure and the first insulation are sandwiched between the substrate and the second insulation. The second insulation has a second thermal expansion coefficient approximately equal to that of the substrate.

Abstract translation: 半导体器件包括衬底，半导体芯片以及第一和第二绝缘体。 衬底具有至少第一区域和第二区域。 半导体芯片结构覆盖第一区域。 第一个绝缘覆盖第二个区域。 第一绝缘体具有与半导体芯片结构大致相等的第一热膨胀系数。 第二绝缘体覆盖半导体芯片结构和第一绝缘体，使得半导体芯片结构和第一绝缘体夹在基板和第二绝缘体之间。 第二绝缘体具有与基板大致相等的第二热膨胀系数。

公开(公告)号：US20120119356A1

公开(公告)日：2012-05-17

申请号：US13106333

申请日：2011-05-12

Applicant: Mitsuhisa WATANABE ,  Ichiro ANJOH

Inventor： Mitsuhisa WATANABE ,  Ichiro ANJOH

IPC: H01L23/498

CPC classification number: H01L21/561 ,  H01L21/6835 ,  H01L21/6836 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/544 ,  H01L24/06 ,  H01L24/16 ,  H01L24/17 ,  H01L24/27 ,  H01L24/90 ,  H01L24/94 ,  H01L2221/68327 ,  H01L2221/68381 ,  H01L2223/54486 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/06136 ,  H01L2224/1134 ,  H01L2224/13099 ,  H01L2224/1601 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/274 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/75 ,  H01L2224/81193 ,  H01L2224/83191 ,  H01L2224/83194 ,  H01L2224/83856 ,  H01L2224/90 ,  H01L2924/00013 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01068 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/3025 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2924/3512 ,  H01L2924/00

Abstract: A semiconductor apparatus includes a semiconductor chip in which a plurality of electrode pads are provided on a main surface, and a plurality of bump electrodes are provided on the electrode pads of the semiconductor chip. The semiconductor apparatus also includes a wired board which is allocated in a side of the main surface of the semiconductor chip, and is positioned in a central area of the main surface of the semiconductor chip so as to be separated from an edge part of the semiconductor chip by at least 50 μm or more. The semiconductor apparatus also includes a plurality of external terminals which are provided on the wired board, and which are electrically connected to a plurality of bump electrodes through wirings of the wired board, and sealing part which is provided between the semiconductor chip and the wired board, is made of underfill material that covers a connection part between the bump electrode and the wiring.

Abstract translation: 半导体装置包括半导体芯片，其中多个电极焊盘设置在主表面上，并且多个凸起电极设置在半导体芯片的电极焊盘上。 半导体装置还包括布线基板，其分配在半导体芯片的主表面的一侧，并且位于半导体芯片的主表面的中心区域中，以与半导体芯片的边缘部分分离 芯片至少50μm以上。 半导体装置还包括设置在布线板上的多个外部端子，并且通过布线板的布线与多个凸起电极电连接，以及设置在半导体芯片和布线板之间的密封部 由底部填充材料制成，其覆盖凸起电极和布线之间的连接部分。

公开(公告)号：US07969019B2

公开(公告)日：2011-06-28

申请号：US12349809

申请日：2009-01-07

Applicant: Mitsuhisa Watanabe ,  Ichiro Anjoh

Inventor： Mitsuhisa Watanabe ,  Ichiro Anjoh

IPC: H01L23/48

CPC classification number: H01L25/0657 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/06136 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/50 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/85

Abstract: Semiconductor device 1 includes: first wiring board 5 provided with a plurality of external terminals 9 on the under surface thereof; first semiconductor chip 3 with the under surface thereof mounted on the upper surface of first wiring board 5; and second semiconductor chip 10 with the under surface thereof mounted on the upper surface of first semiconductor chip 3. On the upper surface of first wiring board 5, connecting pad 6a and connecting pad 6b are provided, while connecting pad 6a is electrically connected with the under surface of first semiconductor chip 3 and connecting pad 6b is arranged closely to an end portion of first semiconductor chip 3. Connecting pad 6a and connecting pad 6b are electrically connected with external terminals 9. Semiconductor device 1 further includes: connecting pad 6c provided as contacting or as being close to an upper end portion of second semiconductor chip 10 while being electrically connected with the upper surface of second semiconductor chip 10, and wire 12 which electrically connects connecting pad 6b and connecting pad 6c.

Abstract translation: 半导体装置1包括：在其下表面上设置有多个外部端子9的第一布线板5; 第一半导体芯片3，其下表面安装在第一布线板5的上表面上; 并且其第二半导体芯片10的下表面安装在第一半导体芯片3的上表面上。在第一布线板5的上表面上设置有连接焊盘6a和连接焊盘6b，而连接焊盘6a与 第一半导体芯片3的下表面和连接焊盘6b靠近第一半导体芯片3的端部设置。连接焊盘6a和连接焊盘6b与外部端子9电连接。半导体装置1还包括：连接焊盘6c， 接触或接近第二半导体芯片10的上端部，同时与第二半导体芯片10的上表面电连接;以及导线12，其将连接焊盘6b和连接焊盘6c电连接。