公开(公告)号：US06943438B2

公开(公告)日：2005-09-13

申请号：US10355448

申请日：2003-01-31

申请人： Min-Young Son ,  Se-Yong Oh ,  Tae-Gyeong Chung

发明人： Min-Young Son ,  Se-Yong Oh ,  Tae-Gyeong Chung

IPC分类号： H01L23/50 ,  G06K19/077 ,  H01L23/538 ,  H01L25/065 ,  H01L25/18 ,  H01L23/28

CPC分类号： G06K19/072 ,  G06K19/07745 ,  H01L23/5388 ,  H01L24/48 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/05599 ,  H01L2224/32145 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2225/0651 ,  H01L2225/06575 ,  H01L2225/06582 ,  H01L2924/00014 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

摘要： In one embodiment, a memory card comprises a card substrate, at least one memory chip attached to the card substrate, a control chip mounted on the memory chip, bonding wires electrically connecting the chips with the card substrate, a passive device attached to the card substrate near the memory chip, and a molded body encapsulating the memory chip, the control chip, the bonding wires and the passive device. In addition, the memory card comprises an adhesive spacer interposed between the same-sized chips to secure a wire loop of the bonding wires.

摘要翻译： 在一个实施例中，存储卡包括卡片基板，附着到卡片基板的至少一个存储器芯片，安装在存储器芯片上的控制芯片，将芯片与卡片基板电连接的接合线，连接到卡片的无源器件 存储芯片附近的衬底，以及封装存储芯片，控制芯片，接合线和无源器件的成型体。 此外，存储卡包括插入在相同尺寸的芯片之间的粘合隔离物，以固定接合线的线环。

公开(公告)号：US07821139B2

公开(公告)日：2010-10-26

申请号：US11946750

申请日：2007-11-28

申请人： Tae-Joo Hwang ,  Eun-Chul Ahn ,  Tae-Gyeong Chung

发明人： Tae-Joo Hwang ,  Eun-Chul Ahn ,  Tae-Gyeong Chung

IPC分类号： H01L31/00

CPC分类号： H01L24/90 ,  H01L23/3171 ,  H01L24/83 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/274 ,  H01L2224/32225 ,  H01L2224/83192 ,  H01L2224/83194 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A flip-chip assembly comprises a semiconductor chip, a substrate, a first buffer layer, a second buffer layer and a conductive bump. The semiconductor chip includes a first region and a second region adjacent to the first region. The substrate is disposed under the semiconductor chip. The first buffer layer is disposed between the first region of the semiconductor chip and the substrate. The second buffer layer is disposed between the second region of the semiconductor chip and the substrate. The conductive bump is formed through the second buffer layer and electrically connects the semiconductor chip to the substrate.

摘要翻译： 倒装芯片组件包括半导体芯片，衬底，第一缓冲层，第二缓冲层和导电凸块。 半导体芯片包括与第一区域相邻的第一区域和第二区域。 衬底设置在半导体芯片下方。 第一缓冲层设置在半导体芯片的第一区域和基板之间。 第二缓冲层设置在半导体芯片的第二区域和基板之间。 导电凸块通过第二缓冲层形成并将半导体芯片电连接到基板。

公开(公告)号：US20060033212A1

公开(公告)日：2006-02-16

申请号：US11253755

申请日：2005-10-20

申请人： Hyeong-Seob Kim ,  Tae-Gyeong Chung

发明人： Hyeong-Seob Kim ,  Tae-Gyeong Chung

IPC分类号： H01L23/48

CPC分类号： H01L24/10 ,  H01L23/481 ,  H01L23/49816 ,  H01L24/13 ,  H01L25/0657 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05548 ,  H01L2224/056 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/14181 ,  H01L2224/16 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2225/06593 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/05124

摘要： A semiconductor chip package includes a semiconductor chip having a through hole extending there through from an active first surface to an inactive second surface. A first conductive pad at least partially surrounds the through hole on the active first surface of the semiconductor chip. The package also includes a printed circuit board having a first surface attached to the inactive second surface of the semiconductor chip, and a second conductive pad aligned with the through hole of the semiconductor chip. A conductive material fills the through hole and contacts the first and second conductive pads.

摘要翻译： 半导体芯片封装包括半导体芯片，该半导体芯片具有从活性第一表面延伸到非活性第二表面的通孔。 第一导电焊盘至少部分地围绕半导体芯片的有源第一表面上的通孔。 封装还包括具有附接到半导体芯片的非活性第二表面的第一表面的印刷电路板和与半导体芯片的通孔对准的第二导电焊盘。 导电材料填充通孔并接触第一和第二导电焊盘。

公开(公告)号：US20120104631A1

公开(公告)日：2012-05-03

申请号：US13344803

申请日：2012-01-06

申请人： Sun-Won Kang ,  Young-Hee Song ,  Tae-Gyeong Chung ,  Nam-Seog Kim ,  Seung-Duk Baek

发明人： Sun-Won Kang ,  Young-Hee Song ,  Tae-Gyeong Chung ,  Nam-Seog Kim ,  Seung-Duk Baek

IPC分类号： H01L23/48

CPC分类号： H01L25/0657 ,  H01L24/06 ,  H01L2224/0401 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49113 ,  H01L2224/85399 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2224/45099 ,  H01L2924/00

摘要： A semiconductor module may include a circuit substrate with a first die on the circuit substrate and a second die on the first die. The first die may include at least one first data input/output pad on a first peripheral portion of the first die and at least one first control/address pad on a third peripheral portion, the third peripheral portion being separate from the first peripheral portion of the first die. The second die may include at least one second data input/output pad on a second peripheral portion and at least one second control/address pad on a fourth peripheral portion. The second peripheral portion of the second die is not overlapped with the first peripheral portion of the first die in plan view. The fourth peripheral portion of the second die overlaps at least a portion of the third peripheral portion of the first die.

摘要翻译： 半导体模块可以包括在电路基板上具有第一裸片的电路基板和在第一裸片上的第二裸片。 第一裸片可以包括在第一裸片的第一周边部分上的至少一个第一数据输入/输出焊盘和第三外围部分上的至少一个第一控制/地址焊盘，第三外围部分与第一外围部分的第一外围部分分离 第一个死亡 第二管芯可以包括在第二外围部分上的至少一个第二数据输入/输出焊盘和第四外围部分上的至少一个第二控制/地址焊盘。 第二模具的第二周边部分在平面图中不与第一模具的第一周边部分重叠。 第二模具的第四周边部分与第一模具的第三周边部分的至少一部分重叠。

公开(公告)号：US07485955B2

公开(公告)日：2009-02-03

申请号：US11077235

申请日：2005-03-11

申请人： In-Ku Kang ,  Seok Goh ,  Jin-Ho Kim ,  Tae-Gyeong Chung ,  Yong-Jae Lee

发明人： In-Ku Kang ,  Seok Goh ,  Jin-Ho Kim ,  Tae-Gyeong Chung ,  Yong-Jae Lee

IPC分类号： H01L23/12 ,  H01L23/053

CPC分类号： H01L24/32 ,  H01L21/78 ,  H01L23/3128 ,  H01L24/05 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L29/0657 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05556 ,  H01L2224/05599 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48471 ,  H01L2224/48479 ,  H01L2224/49175 ,  H01L2224/4945 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/85051 ,  H01L2224/85191 ,  H01L2224/85399 ,  H01L2224/85986 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2225/06582 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01051 ,  H01L2924/01057 ,  H01L2924/01068 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10158 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19041 ,  H01L2224/85186 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/00012 ,  H01L2224/4554

摘要： A variety of non-rectangular IC chips having a stepped or modified periphery or edge profile including one or more recessed or indented peripheral regions are provided for incorporation in modified package configurations, single chip packages and multi-chip assemblies, both stacked and/or planar. In the planar configurations, the recessed regions may be utilized, in cooperation with another appropriately sized IC chip, to increase the packing density of the resulting device. Similarly, in the stacked configuration, the recessed regions may be utilized to provide access to bond pads of lower chips and thereby reduce the need for spacers or peripheral thinning techniques and thereby improve the strength of the resulting assembly and/or reduce the overall height of the stacked structure.

摘要翻译： 提供了具有包括一个或多个凹陷或凹入周边区域的阶梯状或改进的周边或边缘轮廓的各种非矩形IC芯片，用于结合到改进的封装结构，单个芯片封装和多芯片组件中，堆叠和/或平面 。 在平面构造中，可以与另一适当尺寸的IC芯片配合使用凹陷区域，以增加所得器件的封装密度。 类似地，在堆叠构造中，凹陷区域可以用于提供对下部芯片的接合焊盘的访问，从而减少对间隔件或外围变薄技术的需要，从而提高所得组件的强度和/或降低总体高度 堆叠结构。

公开(公告)号：US07368811B2

公开(公告)日：2008-05-06

申请号：US11103479

申请日：2005-04-12

申请人： In-Ku Kang ,  Tae-Gyeong Chung ,  Sang-Ho An

发明人： In-Ku Kang ,  Tae-Gyeong Chung ,  Sang-Ho An

IPC分类号： H01L23/02

CPC分类号： H01L25/50 ,  H01L24/32 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/1134 ,  H01L2224/1308 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/78301 ,  H01L2224/83136 ,  H01L2225/0651 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2225/06575 ,  H01L2924/01006 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/00012

摘要： A multi-chip package and method for manufacturing are disclosed. The multi-chip package may include a substrate, a lower semiconductor chip mounted on the substrate, a first electrical connection for electrically connecting the substrate and the lower semiconductor chip, an upper semiconductor chip attached to the lower semiconductor chip and having overhang portions, and at least one bump interposed between the substrate and the overhang portions. The at least one bump may support the overhang portions and may be formed when the first electrical connection is formed.

摘要翻译： 公开了一种多芯片封装和制造方法。 多芯片封装可以包括基板，安装在基板上的下半导体芯片，用于电连接基板和下半导体芯片的第一电连接，附接到下半导体芯片并具有突出部分的上半导体芯片，以及 插入在基板和突出部分之间的至少一个凸块。 所述至少一个凸块可以支撑所述伸出部分并且可以在形成所述第一电连接时形成。

公开(公告)号：US20110294260A1

公开(公告)日：2011-12-01

申请号：US13137260

申请日：2011-08-02

申请人： Tae-Joo Hwang ,  Tae-Gyeong Chung ,  Eun-Chul Ahn

发明人： Tae-Joo Hwang ,  Tae-Gyeong Chung ,  Eun-Chul Ahn

IPC分类号： H01L21/58

CPC分类号： H01L23/481 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/85 ,  H01L24/97 ,  H01L25/03 ,  H01L25/18 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/73207 ,  H01L2224/73265 ,  H01L2224/81801 ,  H01L2224/85 ,  H01L2224/97 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/0401 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： Example embodiments relate to semiconductor packages and methods of forming the same. A semiconductor package according to example embodiments may include a printed circuit board (PCB), a first semiconductor chip mounted on the PCB, and a chip package mounted on the first semiconductor chip. The chip package may be in direct contact with the first semiconductor chip.

公开(公告)号：US20100327439A1

公开(公告)日：2010-12-30

申请号：US12875551

申请日：2010-09-03

申请人： Tae-Joo Hwang ,  Tae-Gyeong Chung ,  Eun-Chul Ahn

发明人： Tae-Joo Hwang ,  Tae-Gyeong Chung ,  Eun-Chul Ahn

IPC分类号： H01L23/485 ,  H01L23/48

CPC分类号： H01L23/49811 ,  H01L23/481 ,  H01L24/06 ,  H01L24/16 ,  H01L24/29 ,  H01L24/31 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/85 ,  H01L24/97 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/0557 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81801 ,  H01L2224/85 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/078 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package includes a first package substrate, a first semiconductor chip disposed on the first package substrate, the semiconductor chip including first through hole vias, and a chip package disposed on the first semiconductor chip, the chip package including a second package substrate and a second semiconductor chip disposed on the second package substrate, wherein a first conductive terminal is disposed on a first surface of the semiconductor chip and a second conductive terminal is disposed on a first surface of the second package substrate, the first conductive terminal disposed on the second conductive terminal.

摘要翻译： 半导体封装包括第一封装衬底，设置在第一封装衬底上的第一半导体芯片，包括第一通孔通孔的半导体芯片和设置在第一半导体芯片上的芯片封装，芯片封装包括第二封装衬底和 设置在所述第二封装基板上的第二半导体芯片，其中，第一导电端子设置在所述半导体芯片的第一表面上，并且第二导电端子设置在所述第二封装基板的第一表面上，所述第一导电端子设置在所述第二封装基板的第二表面上 导电端子。

公开(公告)号：US20080277800A1

公开(公告)日：2008-11-13

申请号：US12149741

申请日：2008-05-07

申请人： Tae-Joo Hwang ,  Tae-Gyeong Chung ,  Eun-Chul Ahn

发明人： Tae-Joo Hwang ,  Tae-Gyeong Chung ,  Eun-Chul Ahn

IPC分类号： H01L23/538 ,  H01L21/60

CPC分类号： H01L23/481 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/85 ,  H01L24/97 ,  H01L25/03 ,  H01L25/18 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/73207 ,  H01L2224/73265 ,  H01L2224/81801 ,  H01L2224/85 ,  H01L2224/97 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/0401 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： Example embodiments relate to semiconductor packages and methods of forming the same. A semiconductor package according to example embodiments may include a printed circuit board (PCB), a first semiconductor chip mounted on the PCB, and a chip package mounted on the first semiconductor chip. The chip package may be in direct contact with the first semiconductor chip.

摘要翻译： 示例性实施例涉及半导体封装及其形成方法。 根据示例实施例的半导体封装可以包括印刷电路板（PCB），安装在PCB上的第一半导体芯片和安装在第一半导体芯片上的芯片封装。 芯片封装可以与第一半导体芯片直接接触。

公开(公告)号：US09484292B2

公开(公告)日：2016-11-01

申请号：US14263385

申请日：2014-04-28

申请人： Tae-Joo Hwang ,  Tae-Gyeong Chung ,  Eun-Chul Ahn

发明人： Tae-Joo Hwang ,  Tae-Gyeong Chung ,  Eun-Chul Ahn

IPC分类号： H01L23/02 ,  H01L23/29 ,  H01L23/498 ,  H01L23/48 ,  H01L25/03 ,  H01L25/065 ,  H01L23/00 ,  H01L25/18

CPC分类号： H01L23/49811 ,  H01L23/481 ,  H01L24/06 ,  H01L24/16 ,  H01L24/29 ,  H01L24/31 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/85 ,  H01L24/97 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/0557 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81801 ,  H01L2224/85 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/078 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package includes a first package substrate, a first semiconductor chip disposed on the first package substrate, the semiconductor chip including first through hole vias, and a chip package disposed on the first semiconductor chip, the chip package including a second package substrate and a second semiconductor chip disposed on the second package substrate, wherein a first conductive terminal is disposed on a first surface of the semiconductor chip and a second conductive terminal is disposed on a first surface of the second package substrate, the first conductive terminal disposed on the second conductive terminal.