公开(公告)号：US08784636B2

公开(公告)日：2014-07-22

申请号：US12314080

申请日：2008-12-03

申请人： Mizuki Nagai ,  Nobutoshi Saito ,  Fumio Kuriyama ,  Akira Fukunaga

发明人： Mizuki Nagai ,  Nobutoshi Saito ,  Fumio Kuriyama ,  Akira Fukunaga

IPC分类号： C25D7/12 ,  C25D5/10 ,  C25D5/08 ,  C25D21/10 ,  C25D5/00

CPC分类号： H01L21/76847 ,  C23C14/046 ,  C23C14/16 ,  C23C14/584 ,  C25D5/003 ,  C25D5/022 ,  C25D5/08 ,  C25D5/10 ,  C25D7/123 ,  C25D17/001 ,  C25D21/10 ,  H01L21/2885 ,  H01L21/76849 ,  H01L21/76879 ,  H05K3/108 ,  H05K3/423 ,  H05K2201/09563 ,  H05K2203/1476

摘要： A method can form a conductive structure, which is useful for three-dimensional packaging with via plugs, in a shorter time by shortening the conventional long plating time that is an impediment to the practical use of electroplating. The method includes forming a conductive film on an entire surface, including interior surfaces of via holes, of a substrate having the via holes formed in the surface; forming a resist pattern at a predetermined position on the conductive film; carrying out first electroplating under first plating conditions, using the conductive film as a feeding layer, thereby filling a first plated film into the via holes; and carrying out second electroplating under second plating conditions, using the conductive film and the first plated film as a feeding layer, thereby allowing a second plated film to grow on the conductive film and the first plated film, both exposed in the resist openings of the resist pattern.

摘要翻译： 一种方法可以形成导电结构，其可用于具有通孔塞的三维封装，在更短的时间内缩短常规的长电镀时间，这是阻碍电镀实际使用的障碍。 该方法包括在具有形成在表面中的通孔的基板的整个表面上形成导电膜，包括通孔的内表面; 在导电膜上的预定位置处形成抗蚀剂图案; 在第一电镀条件下进行第一次电镀，使用导电膜作为供电层，从而将第一镀膜填充到通孔中; 并且在第二电镀条件下进行第二次电镀，使用导电膜和第一镀膜作为供电层，从而允许第二镀膜在导电膜和第一镀膜上生长，两者都暴露在 抗蚀图案

公开(公告)号：US20090139870A1

公开(公告)日：2009-06-04

申请号：US12314080

申请日：2008-12-03

申请人： Mizuki Nagai ,  Nobutoshi Saito ,  Fumio Kuriyama ,  Akira Fukunaga

发明人： Mizuki Nagai ,  Nobutoshi Saito ,  Fumio Kuriyama ,  Akira Fukunaga

IPC分类号： C25D5/02 ,  C25D17/00

CPC分类号： H01L21/76847 ,  C23C14/046 ,  C23C14/16 ,  C23C14/584 ,  C25D5/003 ,  C25D5/022 ,  C25D5/08 ,  C25D5/10 ,  C25D7/123 ,  C25D17/001 ,  C25D21/10 ,  H01L21/2885 ,  H01L21/76849 ,  H01L21/76879 ,  H05K3/108 ,  H05K3/423 ,  H05K2201/09563 ,  H05K2203/1476

摘要： A method can form a conductive structure, which is useful for three-dimensional packaging with via plugs, in a shorter time by shortening the conventional long plating time that is an impediment to the practical use of electroplating. The method includes forming a conductive film on an entire surface, including interior surfaces of via holes, of a substrate having the via holes formed in the surface; forming a resist pattern at a predetermined position on the conductive film; carrying out first electroplating under first plating conditions, using the conductive film as a feeding layer, thereby filling a first plated film into the via holes; and carrying out second electroplating under second plating conditions, using the conductive film and the first plated film as a feeding layer, thereby allowing a second plated film to grow on the conductive film and the first plated film, both exposed in the resist openings of the resist pattern.

摘要翻译： 一种方法可以形成导电结构，其可用于具有通孔塞的三维封装，在更短的时间内缩短常规的长电镀时间，这是阻碍电镀实际使用的障碍。 该方法包括在具有形成在表面中的通孔的基板的整个表面上形成导电膜，包括通孔的内表面; 在导电膜上的预定位置处形成抗蚀剂图案; 在第一电镀条件下进行第一次电镀，使用导电膜作为供电层，从而将第一镀膜填充到通孔中; 并且在第二电镀条件下进行第二次电镀，使用导电膜和第一镀膜作为供电层，从而允许第二镀膜在导电膜和第一镀膜上生长，两者都暴露在 抗蚀图案

公开(公告)号：US20100105154A1

公开(公告)日：2010-04-29

申请号：US12685820

申请日：2010-01-12

申请人： XINMING WANG ,  Daisuke Takagi ,  Akihiko Tashiro ,  Yukio Fukunaga ,  Akira Fukunaga ,  Akira Owatari ,  Yukiko Nishioka

发明人： XINMING WANG ,  Daisuke Takagi ,  Akihiko Tashiro ,  Yukio Fukunaga ,  Akira Fukunaga ,  Akira Owatari ,  Yukiko Nishioka

IPC分类号： H01L21/66 ,  H01L21/46

CPC分类号： H01L21/02068 ,  C23C18/1632 ,  C23C18/1689 ,  C23C18/1844 ,  H01L21/02074 ,  H01L21/288 ,  H01L21/67028 ,  H01L21/76849 ,  H01L21/76874 ,  H01L21/76883

摘要： A substrate processing method can securely form a metal film by electroless plating on an exposed surface of a base metal, such as interconnects, with increased throughput and without the formation of voids in the base metal. The substrate processing method includes: cleaning a surface of a substrate having a base metal formed in the surface with a cleaning solution comprising an aqueous solution of a carboxyl group-containing organic acid or its salt and a surfactant as an additive; bringing the surface of the substrate after the cleaning into contact with a processing solution comprising a mixture of the cleaning solution and a solution containing a catalyst metal ion, thereby applying the catalyst to the surface of the substrate; and forming a metal film by electroless plating on the catalyst-applied surface of the substrate.

摘要翻译： 基板处理方法可以通过在贱金属（例如互连）的暴露表面上通过无电解电镀牢固地形成金属膜，具有增加的生产量并且在母材中不形成空隙。 基板处理方法包括：用包含含羧基的有机酸或其盐和表面活性剂的水溶液作为添加剂的清洗溶液清洗在表面形成的基体金属的基材的表面; 使清洗后的基板的表面与包含清洗液和含有催化剂金属离子的溶液的混合物的处理溶液接触，从而将催化剂施加到基板的表面; 以及通过在基板的催化剂涂覆表面上通过无电镀形成金属膜。

公开(公告)号：US07498261B2

公开(公告)日：2009-03-03

申请号：US11219777

申请日：2005-09-07

申请人： Xinming Wang ,  Daisuke Takagi ,  Akihiko Tashiro ,  Yukio Fukunaga ,  Akira Fukunaga ,  Akira Owatari

发明人： Xinming Wang ,  Daisuke Takagi ,  Akihiko Tashiro ,  Yukio Fukunaga ,  Akira Fukunaga ,  Akira Owatari

IPC分类号： H01L21/44

CPC分类号： H01L21/288 ,  C23C18/1619 ,  C23C18/1669 ,  C23C18/32 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76874

摘要： A metal film-forming method of the present invention can form a metal film having different film qualities in the thickness direction, in a continuous manner using a single processing solution. The metal film-forming method including: providing a substrate having embedded interconnects formed in interconnect recesses provided in a surface of the substrate; and forming a metal film, having different film qualities in the thickness direction, on surfaces of the interconnects in a continuous manner by changing the flow state of a processing solution relative to the surface of the substrate while keeping the surface of the substrate in contact with the processing solution.

摘要翻译： 本发明的金属成膜方法可以使用单一的处理液以连续的方式形成厚度方向的膜质量不同的金属膜。 所述金属成膜方法包括：提供具有形成在所述基板的表面中的互连凹槽中的嵌入式互连的基板; 并且通过在保持基板的表面与基板的表面接触的同时改变处理液相对于基板的表面的流动状态，以连续的方式在相互连接的表面上形成在厚度方向上具有不同膜质量的金属膜 处理方案。

公开(公告)号：US07407821B2

公开(公告)日：2008-08-05

申请号：US10874245

申请日：2004-06-24

申请人： Xinming Wang ,  Daisuke Takagi ,  Akihiko Tashiro ,  Akira Fukunaga

发明人： Xinming Wang ,  Daisuke Takagi ,  Akihiko Tashiro ,  Akira Fukunaga

IPC分类号： H01L21/66

CPC分类号： H01L21/76849 ,  C23C18/1608 ,  C23C18/1675 ,  C23C18/1692 ,  C23C18/1879 ,  H01L21/288 ,  H01L21/76864 ,  H01L21/76874 ,  H01L22/12 ,  H01L22/20 ,  H01L2223/54466

摘要： There is provided a substrate processing method and apparatus which can measure and monitor thickness and/or properties of a film formed on a substrate as needed, and quickly correct a deviation in process conditions, and which can therefore stably provide a product of constant quality. A substrate processing method for processing a substrate having a metal and an insulating material exposed on its surface in such a manner that a film thickness of the metal, with an exposed surface of the metal as a reference plane, is selectively or preferentially changed, including measuring a change in the film thickness and/or a film property of the metal during and/or immediately after processing, and monitoring processing and adjusting processing conditions based on results of this measurement.

摘要翻译： 提供了可以根据需要测量和监测在基板上形成的膜的厚度和/或性能的基板处理方法和装置，并且可以快速地校正工艺条件的偏差，因此可以稳定地提供恒定品质的产品。 一种基板处理方法，用于处理具有金属和绝缘材料的基板，所述基板以其金属的暴露表面作为基准面的方式选择性地或优先地改变的金属的膜厚度包括 测量处理期间和/或紧随其后的金属的膜厚度和/或膜性质的变化，以及基于该测量结果的监测处理和调整处理条件。

公开(公告)号：US20070289604A1

公开(公告)日：2007-12-20

申请号：US11587974

申请日：2005-04-27

申请人： Yukio Fukunaga ,  Akira Susaki ,  Junji Kunisawa ,  Hiroyuki Ueyama ,  Shohei Shima ,  Akira Fukunaga ,  Hideki Tateishi ,  Junko Mine

发明人： Yukio Fukunaga ,  Akira Susaki ,  Junji Kunisawa ,  Hiroyuki Ueyama ,  Shohei Shima ,  Akira Fukunaga ,  Hideki Tateishi ,  Junko Mine

IPC分类号： C23G1/02 ,  B08B3/00 ,  G05D23/00 ,  G05D99/00

CPC分类号： H01L21/76838 ,  H01L21/02063 ,  H01L21/02068 ,  H01L21/67253

摘要： To provide an apparatus and a method capable of supplying a gas containing an evaporated reducing organic compound while strictly controlling the flow rate thereof to process a surface of a metal on a substrate without causing any deterioration of various types of films forming a semiconductor element with a simple apparatus configuration. The apparatus includes a process chamber 10 for keeping a substrate W therein, the process chamber 10 being gastight, an evacuation control system 20 for controlling the pressure in the process chamber 10, and a process gas supply system 30 for supplying a process gas containing a reducing organic compound to the process chamber 10. The process gas supply system 30 has an evaporator 32 keeping liquid material of the reducing organic compound therein and having an evaporating liquid surface S, a process gas pipe 18 for directing the process gas containing the reducing organic compound evaporated in the evaporator 32 into the process chamber 10, and a throttle element 40 disposed in the process gas pipe 18 for controlling the flow rate of the process gas to be supplied to the process chamber 10 by adjusting the opening of the throttle element 40. The opening of the throttle element 40 is so set that the pressure variation in the evaporator 32 can be maintained within a prescribed range.

摘要翻译： 提供一种能够提供含有蒸发还原性有机化合物的气体的装置和方法，同时严格控制其流速来处理基板上的金属表面，而不会导致形成半导体元件的各种类型的膜的劣化 简单的设备配置。 该装置包括用于将基板W保持在其中的处理室10，气密的处理室10，用于控制处理室10中的压力的​​抽空控制系统20以及用于提供含有 将有机化合物还原成处理室10。 工艺气体供给系统30具有：蒸发器32，其中还原有机化合物的液体材料保持在其中并具有蒸发的液体表面S;一个工艺气体管道18，用于将含有在蒸发器32中蒸发的还原性有机化合物的工艺气体引导到过程 设置在处理气体管道18中的节流元件40，用于通过调节节流元件40的开口来控制供给处理室10的处理气体的流量。 节流元件40的开度被设定为使得蒸发器32中的压力变化可以保持在规定范围内。

公开(公告)号：US20070254558A1

公开(公告)日：2007-11-01

申请号：US11661141

申请日：2005-08-26

申请人： Masako Kodera ,  Yoshihiro Mochizuki ,  Akira Fukuda ,  Akira Kodera ,  Hirokuni Hiyama ,  Manabu Tsujimura ,  Kazuto Hirokawa ,  Akira Fukunaga

发明人： Masako Kodera ,  Yoshihiro Mochizuki ,  Akira Fukuda ,  Akira Kodera ,  Hirokuni Hiyama ,  Manabu Tsujimura ,  Kazuto Hirokawa ,  Akira Fukunaga

IPC分类号： B24B37/04 ,  H01L21/00

CPC分类号： H01L21/6708 ,  B24B37/005 ,  B24B37/042 ,  B24B37/046 ,  B24B49/006 ,  B24B57/02

摘要： A polishing apparatus (30) has a polishing surface (32), a top ring (36) for holding a wafer (W), motors (46, 56) to move the polishing surface (32) and the wafer (W) relative to each other at a relative speed, and a vertical movement mechanism (54) to press the wafer (W) against the polishing surface (32) under a pressing pressure. The polishing apparatus (30) also has a controller (44) to adjust a polishing condition in a non-Preston range in which a polishing rate is not proportional to a product of the pressing pressure and the relative speed. The polishing apparatus (30) can simultaneously achieve uniform supply of a chemical liquid to a surface of the wafer (W) and a uniform polishing rate within the surface of the wafer (W).

摘要翻译： 抛光装置（30）具有抛光面（32），用于保持晶片（W）的顶环（36），使抛光面（32）和晶片（W）相对于运动的电机（46,56）相对于 以及垂直移动机构（54），其在压制压力下将晶片（W）压靠在抛光表面（32）上。 抛光装置（30）还具有控制器（44），用于在抛光速率与按压压力与相对速度的乘积不成比例的非普雷斯顿范围内调节抛光状态。 抛光装置（30）可以同时实现向晶片（W）的表面均匀供应化学液体，并且在晶片表面（W）内均匀的研磨速率。

公开(公告)号：US07055535B2

公开(公告)日：2006-06-06

申请号：US10629678

申请日：2003-07-30

申请人： Junji Kunisawa ,  Norio Kimura ,  Kenya Ito ,  Akira Fukunaga ,  Yuuki Inoue ,  Hiroshi Tomita ,  Soichi Nadahara ,  Motoyuki Sato

发明人： Junji Kunisawa ,  Norio Kimura ,  Kenya Ito ,  Akira Fukunaga ,  Yuuki Inoue ,  Hiroshi Tomita ,  Soichi Nadahara ,  Motoyuki Sato

IPC分类号： B08B3/08 ,  B25B11/00 ,  H01L21/306

CPC分类号： H01L21/6838 ,  Y10S134/902 ,  Y10T279/11

摘要： A holding unit holds a substrate to enable a surface of the substrate to be processed. The unit has a vacuum suction member that comes into contact with a peripheral portion of the surface of the substrate and sucks the substrate. A processing apparatus holds the wafer stably and allows an edge, a bevel portion and/or a back surface of the wafer to be processed.

摘要翻译： 保持单元保持基板以使得能够处理基板的表面。 该单元具有与基板的表面的周边部分接触并吸附基板的真空吸附构件。 处理装置稳定地保持晶片，并且允许晶片的边缘，斜面部分和/或背面被处理。

公开(公告)号：US20060086618A1

公开(公告)日：2006-04-27

申请号：US11254789

申请日：2005-10-21

申请人： Akira Fukunaga ,  Manabu Tsujimura

发明人： Akira Fukunaga ,  Manabu Tsujimura

IPC分类号： C25D5/02

CPC分类号： H01L21/76873 ,  C25D7/123 ,  C25D17/001 ,  H01L21/288 ,  H01L21/32115 ,  H01L21/32125 ,  H01L21/76849 ,  H01L21/76877

摘要： An interconnects-forming method can form a film of interconnect material, having a sufficient adhesion, by electroplating uniformly on an entire surface of a substrate and thus can form highly-reliable embedded interconnects even when the design rule is strict, and which can remove an extra interconnect material at a lower pressure. The interconnects-forming method, including: forming a conductive film on a surface of a substrate having interconnect recesses formed in an insulating film, said conductive film being insoluble in an electrolytic plating solution for the formation of a film of an interconnect material; forming a film of the interconnect material by electroplating on a surface of the conductive film serving as a seed film while filling the interconnect recesses with the interconnect material; and removing an extra interconnect material of the film formed on the conductive film, thereby forming interconnects of the interconnect material embedded in the interconnect recesses.

摘要翻译： 互连形成方法可以通过均匀地电镀在基板的整个表面上形成具有足够的粘附性的互连材料的膜，并且因此即使设计规则是严格的也可以形成高度可靠的嵌入式互连，并且可以去除 额外的互连材料在较低的压力。 所述互连形成方法包括：在具有形成在绝缘膜中的互连凹槽的基板的表面上形成导电膜，所述导电膜不溶于用于形成互连材料膜的电解电镀液; 在用所述互连材料填充所述互连凹槽的同时，通过电镀在所述导电膜的表面上形成所述互连材料的膜; 以及除去形成在导电膜上的膜的额外互连材料，从而形成嵌入在互连凹槽中的互连材料的互连。

公开(公告)号：US20050254051A1

公开(公告)日：2005-11-17

申请号：US11128364

申请日：2005-05-13

申请人： Shohei Shima ,  Akira Fukunaga

发明人： Shohei Shima ,  Akira Fukunaga

IPC分类号： H01L21/304 ,  B24B49/03 ,  B24B49/12 ,  G01B11/06 ,  G01J4/00 ,  G01N21/21

CPC分类号： B24B49/03 ,  B24B37/042 ,  B24B49/12 ,  G01B11/0641 ,  G01N21/211

摘要： A method for polishing a thin film formed on a substrate includes planarizing a thin film formed on a reference substrate by a CMP process such that the thin film remains on the reference substrate. After the planarizing, the thin film is cleaned, and then values of Δ and Ψ with respect to the cleaned thin film are measured by ellipsometry. A physical property of the thin film is determined based on the Δ and Ψ which have been measured by ellipsometry, and a polishing condition for an other substrate having a thin film to be polished is set based on physical property data which are obtained by the determining of the physical property.

摘要翻译： 用于抛光形成在基板上的薄膜的方法包括通过CMP工艺平坦化在参考基板上形成的薄膜，使得薄膜保留在参考基板上。 在平坦化之后，清洁薄膜，然后通过椭偏仪测量相对于清洁的薄膜的Delta和Psi值。 基于通过椭偏仪测量的Delta和Psi来确定薄膜的物理性质，并且基于通过确定获得的物理特性数据来设置具有待抛光薄膜的另一基板的抛光条件 的物理财产。