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公开(公告)号：US5726482A
公开(公告)日：1998-03-10
申请号：US319906
申请日：1994-10-07
IPC分类号： G01R1/04 , G01R1/06 , G01R31/28 , H01L21/48 , H01L23/498 , H01L23/538 , H01R29/00 , H01R31/06 , H05K1/00 , H05K1/14 , H05K1/16 , H05K3/06 , H05K3/24 , H05K3/42 , H05K3/46 , H05K7/10 , H01L29/00
CPC分类号： G01R1/04 , H01L21/485 , H01L23/49827 , H01L23/5382 , H01R29/00 , H05K1/0293 , H05K7/1092 , G01R1/06 , G01R31/2863 , H01L2924/0002 , H01R23/70 , H01R31/06 , H05K1/0289 , H05K1/029 , H05K1/0292 , H05K1/0298 , H05K1/141 , H05K1/167 , H05K2201/0305 , H05K2201/09763 , H05K2201/10181 , H05K2201/10212 , H05K2201/10689 , H05K2203/0542 , H05K2203/105 , H05K2203/1115 , H05K2203/173 , H05K2203/175 , H05K3/062 , H05K3/243 , H05K3/429 , H05K3/4611
摘要： A device-under-test card includes a matrix of fuses and/or antifuses formed as part of a multi-layered structure. The matrix of fuses and/or antifuses can be electrically programmed to connect any one of first electrical contacts to any one of second electrical contacts and so allows the device-under-test card to act as a junction between burn-in board traces couplable to signal drivers and/or receivers and burn-in board traces couplable to terminals of a device-under-test. The device-under-test card also includes a discrete resistor or alternatively a resistor ladder that permits a terminal of a device-under-test to be coupled to a power or ground terminal or to any combination of resistances including a short, in addition or as an alternative to any one of various signal drivers and/or receivers.
摘要翻译： 被测器件包括形成为多层结构的一部分的保险丝和/或反熔断矩阵。 保险丝和/或反熔丝的矩阵可以被电编程以将第一电触点中的任何一个连接到第二电触点中的任一个，并且因此允许测试下的卡作为可连接到 信号驱动器和/或接收器以及可以连接到被测器件端子的老化板迹线。 测试卡以下的设备还包括分立电阻器或可选的电阻梯，其允许被测器件的端子耦合到电源或接地端子或电阻的任何组合，包括短路，或另外 作为各种信号驱动器和/或接收器中的任何一个的替代。
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公开(公告)号：US09529920B2
公开(公告)日：2016-12-27
申请号：US14820433
申请日：2015-08-06
申请人： Robert Osann, Jr.
发明人： Robert Osann, Jr.
IPC分类号： G06F17/30
CPC分类号： G06F17/30867 , G06F17/30554 , G06F17/30696 , G06F17/30905 , G06F17/30991
摘要： A system and method for automatically analyzing and characterizing Internet search results and annotating a search results page according to specific characteristics of each webpage located at a URL corresponding to a search result. Such characteristics include the composition of each search results webpage as well as which search term elements are present in a webpage located at a URL corresponding to a search result out of those search term elements that were submitted to a search engine to produce the search results webpage. Further, search results are annotated to indicate which search term elements are present in a descendent webpage of a webpage located at a URL corresponding to a search result. Search results may also be optionally filtered according to specific characteristics of a webpage located at a search results URL such that certain categories of webpage are excluded from being referenced in the displayed search results.
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公开(公告)号：US09386141B2
公开(公告)日：2016-07-05
申请号：US14791423
申请日：2015-07-04
申请人： Robert Osann, Jr.
发明人： Robert Osann, Jr.
CPC分类号： H04M1/72538 , H04W4/025 , H04W4/029 , H04W4/90 , H04W76/50
摘要： Systems and methods are disclosed for tracking the progress of a trip where a person or persons wish to have a third party automatically informed of a delayed return. For long duration trips and/or trips to distant destinations, people typically make provision for having their pets and/or children watched over. However for short trips, they typically do not, especially with respect to their pets. The disclosed methods provide monitoring of a trip's progress such that if a traveler doesn't return home by a certain time, a third party is notified, thus avoiding a prolonged period of time wherein the pets and/or children are unattended, especially in the event of a catastrophic accident. The third party may be notified if an arrival time is predicted to be delayed, and when an actual arrival occurs. Provision is also included for adjusting the trip duration to delay or advance a designated arrival time.
摘要翻译： 公开了系统和方法，用于跟踪旅行的进展情况，其中希望让第三者自动通知延迟返回。 长途旅行和/或到远方目的地的旅行，人们通常会让他们的宠物和/或儿童观看。 然而，对于短途旅行，他们通常不会，特别是对于他们的宠物。 所公开的方法提供对旅行进度的监视，使得如果旅行者不在一定时间内回家，则通知第三方，从而避免长时间的时间，其中宠物和/或儿童是无人值守的，特别是在 发生灾难性事故。 如果预计到达时间延迟，并且实际到达时，可以通知第三方。 还包括用于调整行程持续时间以延迟或提前指定到达时间的规定。
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公开(公告)号：US08122475B2
公开(公告)日：2012-02-21
申请号：US12069877
申请日：2008-02-12
IPC分类号： H04N7/173
CPC分类号： H04N21/4782 , H04N21/4122 , H04N21/422 , H04N21/42204 , H04N21/4227 , H04N21/43615 , H04N21/4438 , H04N21/47202 , H04N21/4828
摘要： Systems and methods are described for remote control of a media server computer from a controller device, typically a laptop computer, where remote operation of the media server, including the selection of videos and other digital media may be performed from the controller while normal TV programming (cable, satellite, or broadcast) is viewed on the TV. Other embodiments describe background operations performed on the controller device, the media server, or both, such that new videos may be located on the web or locally on the LAN while a current video is playing on the media server and viewed on the TV. Methods are also described for more reliably establishing network connections between the controller and media server, and systems and methods are described for implementing a multi-video display on the media server where videos to be displayed on the media server are displayed on and selected by a controller device.
摘要翻译： 描述了用于从控制器设备（通常为笔记本电脑）远程控制媒体服务器计算机的系统和方法，其中媒体服务器的远程操作包括视频和其他数字媒体的选择可以从控制器执行，而正常的电视节目 （有线，卫星或广播）在电视机上观看。 其他实施例描述了在控制器设备，媒体服务器或两者上执行的后台操作，使得当视频正在媒体服务器上播放并且在电视机上观看时，新的视频可能位于网络上或本地LAN上。 还描述了用于更可靠地建立控制器和媒体服务器之间的网络连接的方法，并且描述了系统和方法，用于在媒体服务器上实现要在媒体服务器上显示的视频被显示在媒体服务器上并由其选择的媒体服务器上的多视频显示 控制器设备。
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公开(公告)号：US07241635B1
公开(公告)日：2007-07-10
申请号：US10704850
申请日：2003-11-10
申请人： Robert Osann, Jr.
发明人： Robert Osann, Jr.
IPC分类号： H01L21/44
摘要： A binning method is disclosed for measuring semiconductor devices for certain parameters and placing specific devices into different categories or “bins” according to the measured parameters. Measurable parameters include performance/speed-grading, power consumption, current leakage, and the ability to operate at certain temperature extremes. A method for speed grading semi-custom ASIC devices is specifically described that does not require removing partially completed wafers from the fab line for testing. To speed-grade a new boat of partially completed un-customized wafers, a small number of wafers (1 or 2) are processed to completion while being customized specifically for a customer design requiring only the slowest bin. These wafer(s) are then performance tested and the remaining wafers in the boat are certified according to these results for their performance level and placed in a wafer bank for later use.
摘要翻译： 公开了一种用于测量某些参数的半导体器件并根据所测量的参数将特定器件置于不同类别或“垃圾桶”中的合并方法。 可测量的参数包括性能/速度分级，功耗，电流泄漏以及在某些极端温度下工作的能力。 具体描述了一种用于速度分级的半定制ASIC器件的方法，其不需要从用于测试的制造线生产线中去除部分完成的晶片。 为了对新的部分完成的未定制晶片进行分级，少量晶圆（1或2）被完成处理，同时专门针对仅需要最慢箱的客户设计进行定制。 然后对这些晶片进行性能测试，并根据这些结果验证船上的剩余晶片的性能水平，并将其放置在晶片库中供以后使用。
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公开(公告)号：US07062744B2
公开(公告)日：2006-06-13
申请号：US10655060
申请日：2003-09-03
申请人： Robert Osann, Jr.
发明人： Robert Osann, Jr.
CPC分类号： G06F15/7867 , G06F9/30145 , G06F9/30181 , G06F9/3885 , G06F9/3897 , G06F17/5054
摘要： To serve prototype and initial production requirements, an emulation solution is described where an ASIC semiconductor device die containing primarily fixed functions, for example a DSP processor with programmable instruction interface, is mounted in the same package as a conventional FPGA device—the FPGA in this example implementing custom instructions for DSP algorithm acceleration and connecting primarily to the fixed function device. A fully integrated, single die ASIC solution is then available for migration of designs to higher volume production where some of the field programmable function will be replaced with fixed function. The base wafer for the ASIC device used in the prototype package and base wafer for the volume production ASIC device may be the same.
摘要翻译： 为了提供原型和初始生产要求，描述了一种仿真解决方案，其中主要固定功能的ASIC半导体器件管芯（例如具有可编程指令接口的DSP处理器）安装在与常规FPGA器件相同的封装中 - 此处的FPGA 实现DSP算法加速的自定义指令并主要连接到固定功能设备的示例。 然后，完全集成的单芯片ASIC解决方案可用于将设计迁移到更大批量的生产，其中一些现场可编程功能将被固定功能替代。 用于批量生产ASIC器件的原型封装和基底晶片中的用于ASIC器件的基底晶片可以是相同的。
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公开(公告)号：US06804812B2
公开(公告)日：2004-10-12
申请号：US10458892
申请日：2003-06-10
申请人： Robert Osann, Jr. , Patrick Hallinan , Jung Lee , Shridhar Mukund
发明人： Robert Osann, Jr. , Patrick Hallinan , Jung Lee , Shridhar Mukund
IPC分类号： G06F1750
CPC分类号： H03K19/17708
摘要： A programmable logic array (PLA) in accordance with the invention achieves a maximum amount of depopulation of programmable connections while still implementing a logic function and maintaining flexibility for future reprogramming. In addition, a PLA in accordance with the invention can be built so that no matter what functionality is programmed, performance characteristics for the device are maintained. Further, a PLA in accordance with the invention does not require a regular array structure.
摘要翻译： 根据本发明的可编程逻辑阵列（PLA）实现可编程连接的最大量的减少，同时仍然实现逻辑功能并保持将来重新编程的灵活性。 此外，可以构建根据本发明的PLA，使得无论编程什么功能，维护设备的性能特性。 此外，根据本发明的PLA不需要规则的阵列结构。
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8.发明授权Integrated circuit architecture having an array of test cells providing full controllability for automatic circuit verification 失效具有测试单元阵列的集成电路架构，为自动电路验证提供完全可控性
公开(公告)号：US6150807A
公开(公告)日：2000-11-21
申请号：US249960
申请日：1999-02-12
申请人： Robert Osann, Jr.
发明人： Robert Osann, Jr.
IPC分类号： G01R31/3181 , G01R31/3185 , G11C29/04 , G11C29/24 , G11C29/32 , G01R31/28
CPC分类号： G01R31/3181 , G01R31/318516 , G11C29/04 , G11C29/24 , G11C29/32
摘要： A new circuit architecture is provided for testing digital integrated circuits which allows one to arbitrarily force any combination of logic values to be simultaneously driven onto any combination of internal nets. This allows all of the connections to each internal logic cell, and the logic cell itself, to be verified by applying a set of test patterns to each logic cell individually. In this way, the integrity of the entire device can be verified without having knowledge of the operation of the circuit as a whole.
摘要翻译： 提供了一种用于测试数字集成电路的新电路架构，其允许任意地强制逻辑值的任何组合被同时驱动到内部网的任何组合上。 这允许通过将一组测试图案单独应用于每个逻辑单元来验证每个内部逻辑单元和逻辑单元本身的所有连接。 以这种方式，可以在不了解整个电路的操作的情况下验证整个设备的完整性。
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9.发明授权
公开(公告)号：US5384433A
公开(公告)日：1995-01-24
申请号：US32723
申请日：1993-03-16
CPC分类号： H05K1/0246 , H05K1/0287 , H05K1/0231 , H05K1/181 , H05K2201/09309 , H05K2201/0949 , H05K2201/10022 , H05K2201/10287 , H05K2201/10303 , H05K2201/10363 , H05K2201/10522 , H05K2201/10636 , H05K2201/10689 , H05K2203/1572 , H05K3/222 , H05K3/3447 , H05K3/4046 , Y02P70/611
摘要： A printed circuit board includes an array of conductive pads including component-mounting holes disposed on first and second surfaces thereon. An array of conductive attachment lands arranged in pairs of first and second attachment lands are disposed on the first and second surfaces. The first and second attachment lands are insulated from one another and separated by a distance selected to allow attachment of standard sized components therebetween on the first and second surfaces of said circuit board. First and second conductive power distribution planes are disposed on the first and second surfaces and are insulated from the conductive pads and the second attachment lands disposed thereon. The first attachment land of each pair on the first surface of the circuit board is electrically connected to the first power distribution plane and the first attachment land of each pair on the second surface of the circuit board is electrically connected to the second power distribution plane, and the second attachment land of each pair on the first and second surfaces of the circuit board electrically connected to one of the conductive pads.
摘要翻译： 印刷电路板包括导电焊盘的阵列，其包括设置在其上的第一和第二表面上的部件安装孔。 布置成成对的第一和第二附接平台的导电附着平台阵列设置在第一和第二表面上。 第一和第二附接平台彼此绝缘并且分开一定距离，以允许在所述电路板的第一和第二表面之间连接标准尺寸的部件。 第一和第二导电配电面设置在第一表面和第二表面上，并与导电焊盘和设置在其上的第二附接焊盘绝缘。 电路板的第一表面上的每一对的第一附着平台与第一配电面电连接，并且电路板的第二表面上的每一对的第一安装台电连接到第二配电面， 并且电路板的第一和第二表面上的每一对的第二附接平台电连接到一个导电焊盘。
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10.发明授权
公开(公告)号：US4079251A
公开(公告)日：1978-03-14
申请号：US713854
申请日：1976-08-12
申请人： Robert Osann, Jr.
发明人： Robert Osann, Jr.
CPC分类号： G01D5/36
摘要： An absolute encoding system is provided based on an incremental optical encoder which, together with a low power circuit technology and means for pulsing the light emitter(s) of the encoder (normally the largest power consuming device(s) in such a system) with a signal of low duty cycle and means for sampling the light detector outputs during the appropriate period of response to the emitted light pulses, produces an encoder system having extremely low internal power consumption allowing not only data retention but also data acquisition during periods of isolation from an external power supply by relying on its own relatively small battery-based power source.
摘要翻译： 提供了一种基于增量光学编码器的绝对编码系统，其与低功率电路技术和用于脉冲编码器的光发射器（通常是这种系统中最大的功率消耗装置）的装置一起提供， 低占空比的信号和在对发射的光脉冲的适当的响应周期内采样光检测器输出的装置产生具有极低内部功耗的编码器系统，不仅允许数据保持，而且允许在隔离期间的数据采集 外部电源依靠自己相对较小的电池供电。
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