公开(公告)号：US09053948B2

公开(公告)日：2015-06-09

申请号：US14256232

申请日：2014-04-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyoung-Hee Kim ,  Ho-Ki Lee ,  Gilheyun Choi ,  Kyu-Hee Han ,  Jongwon Hong

IPC: H01L29/06 ,  H01L21/764 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L29/0649 ,  H01L21/764 ,  H01L21/7682 ,  H01L23/5222 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2221/1047 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device can include wiring lines on a substrate and an interlayer insulating structure, between ones of the wiring lines. The wiring lines can include a pore-containing layer that includes a plurality of pores extending away from a surface of the substrate, wherein ones of the pores have respective volumes that increase with a distance from the substrate until reaching an air gap layer above the pore-containing layer and beneath uppermost surfaces of the wiring lines.

Abstract translation: 半导体器件可以包括衬底上的布线和层间绝缘结构，在布线之间。 布线可以包括含孔层，其包括远离衬底表面延伸的多个孔，其中孔中的一些孔具有随着与衬底的距离而增加的体积，直到达到孔的上方的气隙层 并且在布线的最上表面之下。

公开(公告)号：US20170298507A1

公开(公告)日：2017-10-19

申请号：US15398284

申请日：2017-01-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Soyoung Lee ,  Hyunsu Kim ,  Kiju Sohn ,  Kuntack Lee ,  Jongwon Hong

IPC: C23C16/455 ,  H01L27/115 ,  H01L21/768 ,  H01L21/02

CPC classification number: C23C16/45525 ,  C23C16/4481 ,  H01L21/0228 ,  H01L21/76831 ,  H01L27/11556 ,  H01L27/11582

Abstract: A semiconductor fabrication apparatus can include a plurality of reaction containers that can be coupled together to provide a plurality of sequential respective stages in a process of generating a process gas for semiconductor fabrication, where each reaction container can include a respective semiconductor fabrication solid source material in a respective configuration that is different than in others of the reaction containers.

公开(公告)号：US09142489B2

公开(公告)日：2015-09-22

申请号：US13962341

申请日：2013-08-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongwon Hong ,  Hei Seung Kim ,  Kyoung Hee Nam ,  Jongmyeong Lee ,  Gilheyun Choi

IPC: H01L23/48 ,  H01L23/00

CPC classification number: H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/036 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05017 ,  H01L2224/05093 ,  H01L2224/05548 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2224/11334 ,  H01L2224/1146 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48228 ,  H01L2224/48453 ,  H01L2224/48464 ,  H01L2224/4848 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/48465 ,  H01L2924/00012 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: Semiconductor devices are provided. The semiconductor devices may include a non-planar conductive pattern. The non-planar conductive pattern may be on an insulating layer and may contact a connection terminal at a plurality of different heights. Related methods of forming semiconductor devices are also provided.

Abstract translation: 提供半导体器件。 半导体器件可以包括非平面导电图案。 非平面导电图案可以在绝缘层上并且可以在多个不同高度处接触连接端子。 还提供了形成半导体器件的相关方法。

公开(公告)号：US08779547B2

公开(公告)日：2014-07-15

申请号：US13707425

申请日：2012-12-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongwon Hong ,  Insun Park ,  Hei Seung Kim ,  Jongmin Baek

IPC: H01L21/338 ,  H01L27/04 ,  H01L21/288 ,  H01L27/115 ,  H01L27/108 ,  H01L27/105

CPC classification number: H01L21/76877 ,  C25D3/38 ,  C25D5/08 ,  C25D7/123 ,  C25D17/001 ,  H01L21/2885 ,  H01L21/76802 ,  H01L21/76883 ,  H01L23/522 ,  H01L27/04 ,  H01L27/1052 ,  H01L27/10882 ,  H01L27/10894 ,  H01L27/11526 ,  H01L27/11548 ,  H01L27/11573 ,  H01L27/11575 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided are methods of fabricating a semiconductor device and semiconductor devices fabricated thereby. In the methods, dummy recess regions may be formed between cell recess regions and a peripheral circuit region. Due to the presence of the dummy recess regions, it may be possible to reduce a concentration gradient of a suppressor contained in a plating solution near the dummy pattern region, to make the concentration of the suppressor more uniform in the cell pattern region, and to supply an electric current more effectively to the cell pattern region. As a result, a plating layer can be more uniformly formed in the cell pattern region, without void formation therein.

Abstract translation: 提供制造半导体器件的方法和由此制造的半导体器件。 在这些方法中，可以在单元凹槽区域和外围电路区域之间形成虚拟凹部区域。 由于存在虚拟凹部区域，因此可以降低在虚拟图案区域附近的镀液中所含的抑制剂的浓度梯度，使得抑制器的浓度在电池图案区域中更均匀，并且 向电池图案区域更有效地提供电流。 结果，可以在电池图案区域中更均匀地形成镀层，而不形成空穴。

公开(公告)号：US20140042633A1

公开(公告)日：2014-02-13

申请号：US13962341

申请日：2013-08-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongwon Hong ,  Hei Seung Kim ,  Kyoung Hee Nam ,  Jongmyeong Lee ,  Gilheyun Choi

IPC: H01L23/48

CPC classification number: H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/036 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05017 ,  H01L2224/05093 ,  H01L2224/05548 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2224/11334 ,  H01L2224/1146 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48228 ,  H01L2224/48453 ,  H01L2224/48464 ,  H01L2224/4848 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/48465 ,  H01L2924/00012 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: Semiconductor devices are provided. The semiconductor devices may include a non-planar conductive pattern. The non-planar conductive pattern may be on an insulating layer and may contact a connection terminal at a plurality of different heights. Related methods of forming semiconductor devices are also provided.

Abstract translation: 提供半导体器件。 半导体器件可以包括非平面导电图案。 非平面导电图案可以在绝缘层上并且可以在多个不同高度处接触连接端子。 还提供了形成半导体器件的相关方法。

公开(公告)号：US10465290B2

公开(公告)日：2019-11-05

申请号：US15469212

申请日：2017-03-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minjong Kim ,  Seonggil Park ,  Jaebeom Park ,  Jung-soo Yoon ,  Keeyoung Jun ,  Choongrae Cho ,  Jongwon Hong

IPC: C23C16/50 ,  C23C16/04 ,  C23C16/455 ,  C23C16/458 ,  C23C16/52 ,  H01J37/32

Abstract: Disclosed is a substrate processing apparatus. The substrate processing apparatus comprises a process chamber providing an inner space where a substrate is treated, a support unit disposed in the inner space and supporting the substrate, and a gas supply unit providing the inner space with a process gas required for generating plasma. The support unit comprises a base having a top surface on which the substrate is placed, a heater disposed in the base, and a coating layer formed on the top surface of the base.

公开(公告)号：US20140287578A1

公开(公告)日：2014-09-25

申请号：US14297302

申请日：2014-06-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongwon Hong ,  Insun Park ,  Hei Seung Kim ,  Jongmin Baek

IPC: H01L21/768

CPC classification number: H01L21/76877 ,  C25D3/38 ,  C25D5/08 ,  C25D7/123 ,  C25D17/001 ,  H01L21/2885 ,  H01L21/76802 ,  H01L21/76883 ,  H01L23/522 ,  H01L27/04 ,  H01L27/1052 ,  H01L27/10882 ,  H01L27/10894 ,  H01L27/11526 ,  H01L27/11548 ,  H01L27/11573 ,  H01L27/11575 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided are methods of fabricating a semiconductor device and semiconductor devices fabricated thereby. In the methods, dummy recess regions may be formed between cell recess regions and a peripheral circuit region. Due to the presence of the dummy recess regions, it may be possible to reduce a concentration gradient of a suppressor contained in a plating solution near the dummy pattern region, to make the concentration of the suppressor more uniform in the cell pattern region, and to supply an electric current more effectively to the cell pattern region. As a result, a plating layer can be more uniformly formed in the cell pattern region, without void formation therein.

Abstract translation: 提供制造半导体器件的方法和由此制造的半导体器件。 在这些方法中，可以在单元凹槽区域和外围电路区域之间形成虚拟凹部区域。 由于存在虚拟凹部区域，因此可以降低在虚拟图案区域附近的镀液中所含的抑制剂的浓度梯度，使得抑制器的浓度在电池图案区域中更均匀，并且 向电池图案区域更有效地提供电流。 结果，可以在电池图案区域中更均匀地形成镀层，而不形成空穴。

公开(公告)号：US09362091B2

公开(公告)日：2016-06-07

申请号：US14463166

申请日：2014-08-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Soyoung Lee ,  Suho Lee ,  Chang-Yun Lee ,  Ik Soo Kim ,  Juhyun Lee ,  Jongwon Hong

IPC: H01L21/306 ,  C23F1/00 ,  H01J37/32 ,  C23C16/455 ,  C23C16/50

CPC classification number: H01J37/32449 ,  C23C16/45565 ,  C23C16/45574 ,  C23C16/45589 ,  C23C16/45591 ,  C23C16/50 ,  H01J37/32357 ,  H01J37/3244 ,  H01J37/32807

Abstract: A substrate treating apparatus includes a chamber that encloses an internal space; a susceptor in a lower part of the internal space; a shower head in an upper part of the internal space and spaced above the susceptor and that includes a plurality of distribution holes; and a blocker plate assembly that comprises a body having a plurality of intake holes that divides a space between a top wall of the chamber and the shower head into an upper intake space and a lower distribution space, a ring-shaped partition rib on an upper surface of the body, and a ring-shaped distribution unit on a lower surface of the body.

Abstract translation: 基板处理装置包括封闭内部空间的室; 在内部空间的下部的基座; 位于所述内部空间的上部并且在所述基座上方间隔并包括多个分配孔的淋浴喷头; 以及阻挡板组件，其包括具有多个进气孔的主体，所述多个进气孔将所述腔室的顶壁和所述喷淋头之间的空间分成上进气空间和下分配空间，上部的环形分隔肋 身体的表面，以及在身体的下表面上的环形分配单元。

公开(公告)号：US09070752B2

公开(公告)日：2015-06-30

申请号：US14297302

申请日：2014-06-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongwon Hong ,  Insun Park ,  Hei Seung Kim ,  Jongmin Baek

IPC: H01L21/76 ,  H01L21/768 ,  H01L27/04 ,  H01L21/288 ,  H01L27/105 ,  H01L27/108 ,  H01L27/115 ,  H01L23/522 ,  C25D7/12 ,  C25D5/08 ,  C25D17/00 ,  C25D3/38

CPC classification number: H01L21/76877 ,  C25D3/38 ,  C25D5/08 ,  C25D7/123 ,  C25D17/001 ,  H01L21/2885 ,  H01L21/76802 ,  H01L21/76883 ,  H01L23/522 ,  H01L27/04 ,  H01L27/1052 ,  H01L27/10882 ,  H01L27/10894 ,  H01L27/11526 ,  H01L27/11548 ,  H01L27/11573 ,  H01L27/11575 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided are methods of fabricating a semiconductor device and semiconductor devices fabricated thereby. In the methods, dummy recess regions may be formed between cell recess regions and a peripheral circuit region. Due to the presence of the dummy recess regions, it may be possible to reduce a concentration gradient of a suppressor contained in a plating solution near the dummy pattern region, to make the concentration of the suppressor more uniform in the cell pattern region, and to supply an electric current more effectively to the cell pattern region. As a result, a plating layer can be more uniformly formed in the cell pattern region, without void formation therein.

Abstract translation: 提供制造半导体器件的方法和由此制造的半导体器件。 在这些方法中，可以在单元凹槽区域和外围电路区域之间形成虚拟凹部区域。 由于存在虚拟凹部区域，因此可以降低在虚拟图案区域附近的镀液中所含的抑制剂的浓度梯度，使得抑制器的浓度在电池图案区域中更均匀，并且 向电池图案区域更有效地提供电流。 结果，可以在电池图案区域中更均匀地形成镀层，而不形成空穴。

公开(公告)号：US20140312456A1

公开(公告)日：2014-10-23

申请号：US14256232

申请日：2014-04-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyoung-Hee Kim ,  Ho-Ki Lee ,  Gilheyun Choi ,  Kyu-Hee Han ,  Jongwon Hong

IPC: H01L29/06 ,  H01L23/535

CPC classification number: H01L29/0649 ,  H01L21/764 ,  H01L21/7682 ,  H01L23/5222 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2221/1047 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device can include wiring lines on a substrate and an interlayer insulating structure, between ones of the wiring lines. The wiring lines can include a pore-containing layer that includes a plurality of pores extending away from a surface of the substrate, wherein ones of the pores have respective volumes that increase with a distance from the substrate until reaching an air gap layer above the pore-containing layer and beneath uppermost surfaces of the wiring lines.

Abstract translation: 半导体器件可以包括衬底上的布线和层间绝缘结构，在布线之间。 布线可以包括含孔层，其包括远离衬底表面延伸的多个孔，其中孔中的一些孔具有随着与衬底的距离而增加的体积，直到达到孔的上方的气隙层 并且在布线的最上表面之下。