公开(公告)号：US09305897B2

公开(公告)日：2016-04-05

申请号：US14138646

申请日：2013-12-23

Applicant: STATS ChipPAC, Ltd.

Inventor： DaeSik Choi ,  JongHo Kim ,  HyungMin Lee

IPC: H01L21/4763 ,  H01L23/00 ,  H01L21/683 ,  H01L23/498 ,  H01L23/538 ,  H01L23/552 ,  H01L25/065 ,  H01L25/10 ,  H01L25/00 ,  H01L23/522 ,  H01L23/48 ,  H01L23/31 ,  H01L23/367 ,  H05K3/00

CPC classification number: H01L24/82 ,  H01L21/6835 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/3672 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5226 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/95 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68331 ,  H01L2221/68363 ,  H01L2221/68381 ,  H01L2221/68386 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/16225 ,  H01L2224/29 ,  H01L2224/29101 ,  H01L2224/29144 ,  H01L2224/29187 ,  H01L2224/2919 ,  H01L2224/29298 ,  H01L2224/48105 ,  H01L2224/48175 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81005 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81815 ,  H01L2224/95001 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/09701 ,  H01L2924/10329 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/3025 ,  H05K3/0052 ,  H05K3/007 ,  H05K3/0097 ,  H01L2924/01014 ,  H01L2924/05432 ,  H01L2924/054 ,  H01L2924/0542 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2224/81 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/29299 ,  H01L2224/2929 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device includes a wafer level substrate having a plurality of first conductive vias formed through the wafer level substrate. A first semiconductor die is mounted to the wafer level substrate. A first surface of the first semiconductor die includes contact pads oriented toward a first surface of the wafer level substrate. A first encapsulant is deposited over the first semiconductor die. A second semiconductor die is mounted to the wafer level substrate. A first surface of the second semiconductor die includes contact pads oriented toward a second surface of the wafer level substrate opposite the first surface of the wafer level substrate. A second encapsulant is deposited over the second semiconductor die. A plurality of bumps is formed over the plurality of first conductive vias. A second conductive via can be formed through the first encapsulant and connected to the first conductive via. The semiconductor packages are stackable.

Abstract translation: 半导体器件包括具有通过晶片级衬底形成的多个第一导电通孔的晶片级衬底。 第一半导体管芯安装到晶片级衬底。 第一半导体管芯的第一表面包括朝向晶片级衬底的第一表面定向的接触焊盘。 第一密封剂沉积在第一半导体管芯上。 第二半导体管芯安装到晶片级衬底。 第二半导体管芯的第一表面包括朝向与晶片级衬底的第一表面相对的晶片级衬底的第二表面的接触焊盘。 第二密封剂沉积在第二半导体管芯上。 在多个第一导电通孔上形成多个凸点。 可以通过第一密封剂形成第二导电通孔并连接到第一导电通孔。 半导体封装是可堆叠的。

公开(公告)号：US20140110860A1

公开(公告)日：2014-04-24

申请号：US14138646

申请日：2013-12-23

Applicant: STATS ChipPAC, Ltd.

Inventor： DaeSik Choi ,  JongHo Kim ,  HyungMin Lee

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/522

CPC classification number: H01L24/82 ,  H01L21/6835 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/3672 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5226 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/95 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68331 ,  H01L2221/68363 ,  H01L2221/68381 ,  H01L2221/68386 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/16225 ,  H01L2224/29 ,  H01L2224/29101 ,  H01L2224/29144 ,  H01L2224/29187 ,  H01L2224/2919 ,  H01L2224/29298 ,  H01L2224/48105 ,  H01L2224/48175 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81005 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81815 ,  H01L2224/95001 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/09701 ,  H01L2924/10329 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/3025 ,  H05K3/0052 ,  H05K3/007 ,  H05K3/0097 ,  H01L2924/01014 ,  H01L2924/05432 ,  H01L2924/054 ,  H01L2924/0542 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2224/81 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/29299 ,  H01L2224/2929 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device includes a wafer level substrate having a plurality of first conductive vias formed through the wafer level substrate. A first semiconductor die is mounted to the wafer level substrate. A first surface of the first semiconductor die includes contact pads oriented toward a first surface of the wafer level substrate. A first encapsulant is deposited over the first semiconductor die. A second semiconductor die is mounted to the wafer level substrate. A first surface of the second semiconductor die includes contact pads oriented toward a second surface of the wafer level substrate opposite the first surface of the wafer level substrate. A second encapsulant is deposited over the second semiconductor die. A plurality of bumps is formed over the plurality of first conductive vias. A second conductive via can be formed through the first encapsulant and connected to the first conductive via. The semiconductor packages are stackable.

Abstract translation: 半导体器件包括具有通过晶片级衬底形成的多个第一导电通孔的晶片级衬底。 第一半导体管芯安装到晶片级衬底。 第一半导体管芯的第一表面包括朝向晶片级衬底的第一表面定向的接触焊盘。 第一密封剂沉积在第一半导体管芯上。 第二半导体管芯安装到晶片级衬底。 第二半导体管芯的第一表面包括朝向与晶片级衬底的第一表面相对的晶片级衬底的第二表面的接触焊盘。 第二密封剂沉积在第二半导体管芯上。 在多个第一导电通孔上形成多个凸点。 可以通过第一密封剂形成第二导电通孔并连接到第一导电通孔。 半导体封装是可堆叠的。