Variable resistance memory device

    公开(公告)号:US11706931B2

    公开(公告)日:2023-07-18

    申请号:US17230029

    申请日:2021-04-14

    IPC分类号: H10B61/00 H10B63/00

    摘要: A variable resistance memory device including a substrate; horizontal structures spaced apart from each other in a first direction perpendicular to a top surface of the substrate; variable resistance patterns on the horizontal structures, respectively; and conductive lines on the variable resistance patterns, respectively, wherein each of the horizontal structures includes a first electrode pattern, a semiconductor pattern, and a second electrode pattern arranged along a second direction parallel to the top surface of the substrate, and each of the variable resistance patterns is between one of the second electrode patterns and a corresponding one of the conductive lines.

    PROCESS CONTROL METHOD AND PROCESS CONTROL SYSTEM FOR MANUFACTURING SEMICONDUCTOR DEVICE

    公开(公告)号:US20190115527A1

    公开(公告)日:2019-04-18

    申请号:US16107242

    申请日:2018-08-21

    摘要: Provided are process control methods and process control systems. The method includes performing a deposition process on a lot defined by a group of a plurality of wafers, performing a measurement process on the lot to obtain a measured value with respect to at least one wafer among the plurality of wafers, producing a target value of a factor of a process condition in the deposition process by using a difference between the measured value and a reference value, and providing an input value of the factor with respect to a subsequent lot based on the target value. The operation of providing the input value of the factor includes obtaining a previous target value of the factor previously produced with respect to at least one previous lot, and providing a weighted average of the previous target value and the target value as the input value.

    MAGNETIC MEMORY DEVICES
    10.
    发明申请

    公开(公告)号:US20220158085A1

    公开(公告)日:2022-05-19

    申请号:US17358435

    申请日:2021-06-25

    摘要: A magnetic memory device including a magnetic tunnel junction is provided. The magnetic tunnel junction includes a fixed layer, a polarization enhancement structure on the fixed layer, a tunnel barrier layer on the polarization enhancement structure, and a free layer on the tunnel barrier layer, wherein the polarization enhancement structure includes a plurality of polarization enhancement layers and at least one spacer layer which separates the plurality of polarization enhancement layers from each other. A thickness of each of the plurality of polarization enhancement layers is from 5 Å to about 20 Å, and a thickness of the at least one spacer layer is from about 2 Å to about 15 Å.