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    Integrated circuit devices including a vertical memory device
    1.
    发明授权
    Integrated circuit devices including a vertical memory device 有权

    公开(公告)号：US10312191B2

    公开(公告)日：2019-06-04

    申请号：US15923737

    申请日：2018-03-16

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Young-jin Jung ,  Joon-hee Lee

    IPC: H01L23/528 ,  H01L27/11582 ,  H01L27/11556

    Abstract: Provided is an integrated circuit device including a plurality of word lines overlapping each other, in a vertical direction, on a substrate, a plurality of channel structures extending in the vertical direction through the plurality of word lines on an area of the substrate, a plurality of bit line contact pads on the plurality of channel structures, and a plurality or bit lines, wherein the plurality of bit lines include a plurality of first bit lines extending parallel to each other at a first pitch in a center region of the area, and a plurality of second bit lines extending at a second pitch in an edge region of the area, the second pitch being different from the first pitch.

    Integrated circuit devices including a vertical memory device
    3.
    发明授权
    Integrated circuit devices including a vertical memory device 有权

    公开(公告)号：US10811356B2

    公开(公告)日：2020-10-20

    申请号：US16784900

    申请日：2020-02-07

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Young-jin Jung ,  Joon-hee Lee

    IPC: H01L23/00 ,  H01L23/528 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157

    Abstract: Provided is an integrated circuit device including a plurality of word lines overlapping each other, in a vertical direction, on a substrate, a plurality of channel structures extending in the vertical direction through the plurality of word lines on an area of the substrate, a plurality of bit line contact pads on the plurality of channel structures, and a plurality of bit lines, wherein the plurality of bit lines include a plurality of first bit lines extending parallel to each other at a first pitch in a center region of the area, and a plurality of second bit lines extending at a second pitch in an edge region of the area, the second pitch being different from the first pitch.

    Integrated circuit devices including a vertical memory device
    4.
    发明授权
    Integrated circuit devices including a vertical memory device 有权

    公开(公告)号：US10586766B2

    公开(公告)日：2020-03-10

    申请号：US16410266

    申请日：2019-05-13

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Young-jin Jung ,  Joon-hee Lee

    IPC: H01L23/52 ,  H01L23/528 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157

    Abstract: Provided is an integrated circuit device including a plurality of word lines overlapping each other, in a vertical direction, on a substrate, a plurality of channel structures extending in the vertical direction through the plurality of word lines on an area of the substrate, a plurality of bit line contact pads on the plurality of channel structures, and a plurality of bit lines, wherein the plurality of bit lines include a plurality of first bit lines extending parallel to each other at a first pitch in a center region of the area, and a plurality of second bit lines extending at a second pitch in an edge region of the area, the second pitch being different from the first pitch.

    INTEGRATED CIRCUIT DEVICES INCLUDING A VERTICAL MEMORY DEVICE
    5.
    发明申请
    INTEGRATED CIRCUIT DEVICES INCLUDING A VERTICAL MEMORY DEVICE 审中-公开

    公开(公告)号：US20200176375A1

    公开(公告)日：2020-06-04

    申请号：US16784900

    申请日：2020-02-07

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Young-jin Jung ,  Joon-hee Lee

    IPC: H01L23/528 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157

    Abstract: Provided is an integrated circuit device including a plurality of word lines overlapping each other, in a vertical direction, on a substrate, a plurality of channel structures extending in the vertical direction through the plurality of word lines on an area of the substrate, a plurality of bit line contact pads on the plurality of channel structures, and a plurality of bit lines, wherein the plurality of bit lines include a plurality of first bit lines extending parallel to each other at a first pitch in a center region of the area, and a plurality of second bit lines extending at a second pitch in an edge region of the area, the second pitch being different from the first pitch.

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