摘要:
Disclosed is a piezoelectric ceramic composition comprising a PZT piezoelectric composition, a B-site of which is substituted with a certain material, and chromium oxide, and a piezoelectric device using the piezoelectric ceramic composition. The piezoelectric ceramic composition has good heat resistance and frequency stability, and reduces a leakage current. There is provided the piezoelectric ceramic composition comprising a main component expressed by Pb[(Co1/2W1/2)xTi1−x−yZry]O3 (wherein, 0.001≦x≦0.04, and 0.35 ≦y≦0.55), Cr2O3 in an amount of 0.01 to 2 wt %, MnO2 in an amount of 0.1 to 0.5 wt %, and an additive in an amount of 0.01 to 2.0 wt %, based on the total weight of the piezoelectric ceramic composition, in which the additive is selected from the group consisting of CoO, MgO, ZnO, Al2O3, Fe2O3, Sb2O3, SnO2, CeO2, Nb2O5, V2O5 and WO3, and mixtures thereof. The piezoelectric ceramic composition satisfies piezoelectric properties such as kp and Qm needed for a piezoelectric material, and is 320° C. or higher in phase transition temperature, ±30 ppm/° C. in TCF, and 0.1% or less in oscillation frequency change after reflow; and the piezoelectric ceramic composition also has good piezoelectric properties such that the leakage current is reduced.
摘要:
The present invention provides a piezoelectric ceramic composition having the formula: {[Pb(1−1.5x)±(0˜0.2)Lax][Ti(1−y−z)MnyCuz]O3} which meets the requirements: 0.02
摘要翻译:本发明提供一种具有以下结构的压电陶瓷组合物:符合要求的{[Pb(1-1.5×)±(0〜0.2)Lax] [Ti(1-yz)MnyCuz] O 3}:0.02
摘要:
Disclosed is a trench substrate, which includes a first insulating layer having trenches formed therein, a second insulating layer disposed on a lower surface of the first insulating layer and having laser processability inferior to that of the first insulating layer, and a negative pattern formed in the trenches, and in which the second insulating layer having laser processability inferior to that of the first insulating layer functions as a stopper, so that the trenches having the same shape are formed in the first insulating layer, thus enabling the formation of a fine and uniform circuit pattern. A method of fabricating the trench substrate is also provided.
摘要:
Disclosed is a PCB including an embedded resistor and a method of fabricating the same. The PCB includes a plurality of circuit layers in which circuit patterns are formed. A plurality of insulating layers is each interposed between the circuit layers. The embedded resistor is made of a resistive material and received in a receiving hole formed in the plurality of circuit layers and the plurality of insulating layers such that walls defining the receiving hole extends from one of the circuit layers to another circuit layer. The receiving hole has a closed section, and a conductive material is plated on the opposite walls of the walls defining the receiving hole.
摘要:
Disclosed herein is a coreless substrate having filled via pads and a method of manufacturing the same. Insulating layers are formed on both sides of a build-up layer, and via-pads are embedded in the insulating layers such that the via-pads are flush with the insulating layers. The via pads are not separated from a substrate, and thus reliability of the pads is increased. Flatness of bumps is increased, and thus bonding of flip chips becomes easy.
摘要:
Disclosed herein is a Printed Circuit Board (PCB) having embedded resistors and a method of manufacturing the same, in which contact pads are formed by filling via holes formed on electrode pads with oxidation-resistant conductive material, and resistors are formed on the contact pads. Accordingly, erosion that occurs between the electrode pads and the resistors can be prevented using the contact pads made of oxidation-resistant conductive material, and connections between circuits also can be realized. Furthermore, resistors are formed on a flat plane without any difference in height, attributable to the electrode pads, and thus differences between the resistance values of the built-in resistors can be greatly reduced.
摘要:
Disclosed herein is a coreless substrate having filled via pads and a method of manufacturing the same. Insulating layers are formed on both sides of a build-up layer, and via-pads are embedded in the insulating layers such that the via-pads are flush with the insulating layers. The via pads are not separated from a substrate, and thus reliability of the pads is increased. Flatness of bumps is increased, and thus bonding of flip chips becomes easy.
摘要:
Disclosed herein are a semiconductor package and a method for manufacturing the same. The method includes preparing a substrate having one surface and the other surface; mounting a semiconductor device mounted on one surface of the substrate; forming external connection terminals on the other surface of the substrate; forming a warpage preventing layer formed on one surface of the substrate or the other surface of the substrate; and performing a reflow process on the substrate.