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    SEMICONDUCTOR PACKAGE HAVING THROUGH ELECTRODES THAT REDUCE LEAKAGE CURRENT AND METHOD FOR MANUFACTURING THE SAME
    1.
    发明申请
    SEMICONDUCTOR PACKAGE HAVING THROUGH ELECTRODES THAT REDUCE LEAKAGE CURRENT AND METHOD FOR MANUFACTURING THE SAME 有权
    具有降低泄漏电流的电极的半导体封装及其制造方法

    公开(公告)号：US20120045895A1

    公开(公告)日：2012-02-23

    申请号：US13286376

    申请日：2011-11-01

    申请人： Seung Hee JO ,  Sung Cheol KIM ,  Sung Min KIM

    发明人： Seung Hee JO ,  Sung Cheol KIM ,  Sung Min KIM

    IPC分类号： H01L21/283

    CPC分类号： H01L25/0657 ,  H01L21/76898 ,  H01L23/3128 ,  H01L25/50 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/15311

    摘要： A stacked semiconductor package having through electrodes that exhibit a reduced leakage current and a method of making the same are presented. The stacked semiconductor package includes a semiconductor chip, through-holes, and a current leakage prevention layer. The semiconductor chip has opposing first and second surfaces. The through-holes pass entirely through the semiconductor chip and are exposed at the first and second surfaces. A polarized part is formed on at least one of the first and second surfaces of the semiconductor chip. The through-electrodes are disposed within the through-holes. The current leakage prevention layer covers the polarized part and exposes ends of the through-electrodes.

    摘要翻译： 本发明提供一种具有通过电极显示泄漏电流减小的叠层半导体封装及其制造方法。 叠层半导体封装包括半导体芯片，通孔和防止漏电流层。 半导体芯片具有相对的第一和第二表面。 通孔完全穿过半导体芯片，并在第一和第二表面露出。 偏振部分形成在半导体芯片的第一和第二表面中的至少一个上。 通孔设置在通孔内。 电流防漏层覆盖极化部分并暴露通孔的端部。

    SEMICONDUCTOR PACKAGE HAVING THROUGH ELECTRODES THAT REDUCE LEAKAGE CURRENT AND METHOD FOR MANUFACTURING THE SAME
    2.
    发明申请
    SEMICONDUCTOR PACKAGE HAVING THROUGH ELECTRODES THAT REDUCE LEAKAGE CURRENT AND METHOD FOR MANUFACTURING THE SAME 审中-公开
    具有降低泄漏电流的电极的半导体封装及其制造方法

    公开(公告)号：US20110031609A1

    公开(公告)日：2011-02-10

    申请号：US12640102

    申请日：2009-12-17

    申请人： Seung Hee JO ,  Sung Cheol KIM ,  Sung Min KIM

    发明人： Seung Hee JO ,  Sung Cheol KIM ,  Sung Min KIM

    IPC分类号： H01L23/52 ,  H01L21/44

    CPC分类号： H01L25/0657 ,  H01L21/76898 ,  H01L23/3128 ,  H01L25/50 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/15311

    摘要： A stacked semiconductor package having through electrodes that exhibit a reduced leakage current and a method of making the same are presented. The stacked semiconductor package includes a semiconductor chip, through-holes, and a current leakage prevention layer. The semiconductor chip has opposing first and second surfaces. The through-holes pass entirely through the semiconductor chip and are exposed at the first and second surfaces. A polarized part is formed on at least one of the first and second surfaces of the semiconductor chip. The through-electrodes are disposed within the through-holes. The current leakage prevention layer covers the polarized part and exposes ends of the through-electrodes.

    摘要翻译： 本发明提供一种具有通过电极显示泄漏电流减小的叠层半导体封装及其制造方法。 叠层半导体封装包括半导体芯片，通孔和防止漏电流层。 半导体芯片具有相对的第一和第二表面。 通孔完全穿过半导体芯片，并在第一和第二表面露出。 偏振部分形成在半导体芯片的第一和第二表面中的至少一个上。 通孔设置在通孔内。 电流防漏层覆盖极化部分并暴露通孔的端部。

    METHOD FOR FABRICATING VIA HOLE AND THROUGH-SILICON VIA
    4.
    发明申请
    METHOD FOR FABRICATING VIA HOLE AND THROUGH-SILICON VIA 审中-公开
    通过孔和通过硅制造的方法

    公开(公告)号：US20120129341A1

    公开(公告)日：2012-05-24

    申请号：US13187845

    申请日：2011-07-21

    申请人： Seung Hee JO ,  Seong Cheol KIM

    发明人： Seung Hee JO ,  Seong Cheol KIM

    IPC分类号： H01L21/28 ,  H01L21/311

    CPC分类号： H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method for fabricating a via hole includes forming a first mask pattern on a first surface of a wafer exposing a portion of the first surface of the wafer, forming a passivation region within the wafer by implanting impurities into the exposed portion of the wafer using the first mask pattern as an ion implantation barrier layer, forming an etching stop layer on the first surface of the wafer including the passivation regions, forming a second mask pattern on a second surface of the wafer faces away from the first surface of the wafer, wherein the second mask pattern exposes a portion of the second surface of the wafer over an area between the passivation regions, and forming a via hole by etching the wafer using the second mask pattern as an etching mask.

    摘要翻译： 一种用于制造通孔的方法包括在晶片的第一表面上形成第一掩模图案，该第一表面露出晶片的第一表面的一部分，通过将晶体中的杂质注入到晶片的暴露部分中，通过使用 第一掩模图案作为离子注入阻挡层，在包括钝化区的晶片的第一表面上形成蚀刻停止层，在晶片的第二表面上形成第二掩模图案，远离晶片的第一表面，其中 第二掩模图案将晶片的第二表面的一部分暴露在钝化区之间的区域上，并且使用第二掩模图案作为蚀刻掩模通过蚀刻晶片形成通孔。