公开(公告)号：US08610006B2

公开(公告)日：2013-12-17

申请号：US12604907

申请日：2009-10-23

申请人： Shih-Ping Hsu ,  Kun-Chen Tsai ,  Micallaef Ivan

发明人： Shih-Ping Hsu ,  Kun-Chen Tsai ,  Micallaef Ivan

IPC分类号： H01L23/28

CPC分类号： H05K9/0084 ,  B81B7/0061 ,  B81B7/0064 ,  B81B2201/0257 ,  H04R19/005

摘要： A lid for a micro-electro-mechanical device and a method for fabricating the same are provided. The lid includes a board with opposite first and second surfaces and a first conductor layer. The first surface has a first metal layer thereon. The first metal layer and the board have a recess formed therein. The recess has a bottom surface and a side surface adjacent thereto. The first conductor layer is formed on the first metal layer and the bottom and side surfaces of the recess. The shielding effect of the side surface of the board is enhanced because of the recess integral to the board, the homogeneous bottom and side surfaces of the recess, and the first conductor layer covering the first metal layer, the bottom and side surfaces of the recess.

摘要翻译： 提供了一种微机电装置用盖及其制造方法。 盖子包括具有相对的第一和第二表面的板和第一导体层。 第一表面上具有第一金属层。 第一金属层和板具有形成在其中的凹部。 凹部具有底表面和与其相邻的侧表面。 第一导体层形成在第一金属层和凹部的底部和侧表面上。 板的侧面的屏蔽效果由于与板的整体凹部，凹部的均匀的底部和侧表面以及覆盖第一金属层的第一导体层，凹部的底部和侧表面而增强 。

公开(公告)号：US20100108345A1

公开(公告)日：2010-05-06

申请号：US12604907

申请日：2009-10-23

申请人： Shih-Ping Hsu ,  Kun-Chen Tsai ,  Micallaef Ivan

发明人： Shih-Ping Hsu ,  Kun-Chen Tsai ,  Micallaef Ivan

IPC分类号： H05K5/00 ,  H05K13/00 ,  B05D5/12

CPC分类号： H05K9/0084 ,  B81B7/0061 ,  B81B7/0064 ,  B81B2201/0257 ,  H04R19/005

摘要： A lid for a micro-electro-mechanical device and a method for fabricating the same are provided. The lid includes a board with opposite first and second surfaces and a first conductor layer. The first surface has a first metal layer thereon. The first metal layer and the board have a recess formed therein. The recess has a bottom surface and a side surface adjacent thereto. The first conductor layer is formed on the first metal layer and the bottom and side surfaces of the recess. The shielding effect of the side surface of the board is enhanced because of the recess integral to the board, the homogeneous bottom and side surfaces of the recess, and the first conductor layer covering the first metal layer, the bottom and side surfaces of the recess. Hence, the shielding effect upon the micro-electro-mechanical device is enhanced.

摘要翻译： 提供了一种微机电装置用盖及其制造方法。 盖子包括具有相对的第一和第二表面的板和第一导体层。 第一表面上具有第一金属层。 第一金属层和板具有形成在其中的凹部。 凹部具有底表面和与其相邻的侧表面。 第一导体层形成在第一金属层和凹部的底部和侧表面上。 板的侧面的屏蔽效果由于与板的整体凹部，凹部的均匀的底部和侧表面以及覆盖第一金属层的第一导体层，凹部的底部和侧表面而增强 。 因此，增强了对微机电装置的屏蔽效果。

公开(公告)号：US07485970B2

公开(公告)日：2009-02-03

申请号：US11448420

申请日：2006-06-06

申请人： Shih-Ping Hsu ,  Kun-Chen Tsai

发明人： Shih-Ping Hsu ,  Kun-Chen Tsai

IPC分类号： H01L23/48

CPC分类号： H01L24/02 ,  H01L21/4846 ,  H01L21/486 ,  H01L23/3128 ,  H01L23/498 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/0401 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/1532 ,  H05K1/113 ,  H05K3/108 ,  H05K3/243 ,  H05K3/28 ,  H05K3/423 ,  H05K2201/0394 ,  H05K2201/09563 ,  H05K2203/0574 ,  H01L2924/00015 ,  H01L2224/05599 ,  H01L2924/00

摘要： A semiconductor package substrate and a method for fabricating the same are proposed. An insulating layer has a plurality of blind vias to expose inner traces underneath the insulating layer. A conductive film is formed on the insulating layer and over the bind vias. A first resist is formed on the conductive film, having openings to expose parts of the conductive film. A patterned trace layer including a plurality of contact pads is formed in the openings and the blind vias to form conductive vias, with at least one contact pad electrically connected to one conductive via. A second resist is formed on the patterned trace layer without covering the contact pads. A metal barrier layer is formed on the contact pads. Finally, the first and second resists and parts of the conductive film covered the first resist are removed.

摘要翻译： 提出了半导体封装基板及其制造方法。 绝缘层具有多个盲孔以暴露绝缘层下方的内部迹线。 在绝缘层上和结合通孔上形成导电膜。 第一抗蚀剂形成在导电膜上，具有露出导电膜部分的开口。 在开口和盲孔中形成包括多个接触焊盘的图案化迹线层，以形成导电通路，其中至少一个接触焊盘电连接到一个导电通孔。 在图案化的迹线层上形成第二抗蚀剂而不覆盖接触焊盘。 在接触焊盘上形成金属阻挡层。 最后，去除覆盖第一抗蚀剂的导电膜的第一和第二抗蚀剂和部分。

公开(公告)号：US20050082672A1

公开(公告)日：2005-04-21

申请号：US10876475

申请日：2004-06-28

申请人： Shih-Ping Hsu ,  Kun-Chen Tsai

发明人： Shih-Ping Hsu ,  Kun-Chen Tsai

IPC分类号： H01L21/48 ,  H01L23/498 ,  H05K3/06 ,  H05K3/10 ,  H05K3/24 ,  H05K3/28 ,  H05K3/38 ,  H01L23/48

CPC分类号： H01L23/49866 ,  H01L21/4846 ,  H01L2924/0002 ,  H05K3/062 ,  H05K3/108 ,  H05K3/244 ,  H05K3/28 ,  H05K3/388 ,  H05K2203/054 ,  H05K2203/0597 ,  H01L2924/00

摘要： A circuit barrier structure of a semiconductor packaging substrate and a method for fabricating the same, forming a metal conductive layer on an insulating layer of the substrate and a patterned resist layer on the metal conductive layer. The patterned resist layer has a plurality of holes to expose predetermined parts of the metal conductive layer. A metal barrier layer is formed on the resist layer and in the holes. A patterned circuit layer is electroplated in the holes of the resist layer after removing the metal barrier layer on the resist layer. The resist layer and the metal conductive layer underneath the resist layer are removed. Another metal barrier layer can be formed on the circuit layer. The patterned circuit layer is covered by the metal barrier layers to prevent damage from etching to the circuit layer and inhibit migration of metal particles in the circuit layer.

摘要翻译： 半导体封装基板的电路阻挡结构及其制造方法，在基板的绝缘层上形成金属导电层，在金属导电层上形成图案化的抗蚀剂层。 图案化的抗蚀剂层具有多个孔以暴露金属导电层的预定部分。 在抗蚀剂层和孔中形成金属阻挡层。 在除去抗蚀剂层上的金属阻挡层之后，在抗蚀剂层的孔中电镀图案化的电路层。 去除抗蚀剂层下面的抗蚀剂层和金属导电层。 可以在电路层上形成另一金属阻挡层。 图案化电路层被金属阻挡层覆盖，以防止腐蚀到电路层的损伤并且抑制金属颗粒在电路层中的迁移。

公开(公告)号：US07174631B2

公开(公告)日：2007-02-13

申请号：US10923711

申请日：2004-08-24

申请人： Shih-Ping Hsu ,  Kun-Chen Tsai

发明人： Shih-Ping Hsu ,  Kun-Chen Tsai

IPC分类号： H01K3/22

CPC分类号： H01L24/11 ,  H01L23/3121 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05026 ,  H01L2224/05155 ,  H01L2224/05572 ,  H01L2224/05611 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/13099 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49135 ,  Y10T29/49139 ,  Y10T29/49144 ,  Y10T29/49155 ,  Y10T29/49158 ,  Y10T29/49222 ,  H01L2924/00 ,  H01L2924/00014

摘要： An electrical connection terminal of an embedded chip and a method for fabricating the same are disclosed. An insulating layer is provided on a circuit board integrated with a chip and has a plurality of first openings for exposing a conductive pad of the chip. A first metal layer is formed on the conductive pad, and a conductive layer if formed on surfaces of the first metal layer, the insulating layer and the first openings. A patterned resist layer is formed on the conductive layer and has a plurality of second openings for exposing a part of the conductive layer corresponding to the condictive pad of the chip. A second metal layer is formed on the exposed part of the conductive layer by an electroplating process. Thus, the fabrication of conductive structure of the conductive pad of the ship and build-up of conductive circuits on the circuit board are integrated simultaneously.

摘要翻译： 公开了嵌入式芯片的电连接端子及其制造方法。 绝缘层设置在与芯片集成的电路板上，并且具有用于暴露芯片的导电焊盘的多个第一开口。 第一金属层形成在导电焊盘上，如果形成在第一金属层，绝缘层和第一开口的表面上，则形成导电层。 图案化的抗蚀剂层形成在导电层上，并且具有多个第二开口，用于暴露对应于芯片的引导垫的导电层的一部分。 通过电镀工艺在导电层的暴露部分上形成第二金属层。 因此，船舶的导电焊盘的导电结构的制造和电路板上的导电电路的积聚被同时集成。

公开(公告)号：US07081402B2

公开(公告)日：2006-07-25

申请号：US10695356

申请日：2003-10-27

申请人： Shih-Ping Hsu ,  Kun-Chen Tsai

发明人： Shih-Ping Hsu ,  Kun-Chen Tsai

IPC分类号： H01L21/44

CPC分类号： H01L24/02 ,  H01L21/4846 ,  H01L21/486 ,  H01L23/3128 ,  H01L23/498 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/0401 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/1532 ,  H05K1/113 ,  H05K3/108 ,  H05K3/243 ,  H05K3/28 ,  H05K3/423 ,  H05K2201/0394 ,  H05K2201/09563 ,  H05K2203/0574 ,  H01L2924/00015 ,  H01L2224/05599 ,  H01L2924/00

摘要： A semiconductor package substrate and a method for fabricating the same are proposed. An insulating layer has a plurality of blind vias to expose inner traces underneath the insulating layer. A conductive film is formed on the insulating layer and over the bind vias. A first resist is formed on the conductive film, having openings to expose parts of the conductive film. A patterned trace layer including a plurality of contact pads is formed in the openings and the blind vias to form conductive vias, with at least one contact pad electrically connected to one conductive via. A second resist is formed on the patterned trace layer without covering the contact pads. A metal barrier layer is formed on the contact pads. Finally, the first and second resists and parts of the conductive film covered the first resist are removed.

公开(公告)号：US20050224976A1

公开(公告)日：2005-10-13

申请号：US10923711

申请日：2004-08-24

申请人： Shih-Ping Hsu ,  Kun-Chen Tsai

发明人： Shih-Ping Hsu ,  Kun-Chen Tsai

IPC分类号： H01L21/60 ,  H01L21/768 ,  H01L29/84

CPC分类号： H01L24/11 ,  H01L23/3121 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05026 ,  H01L2224/05155 ,  H01L2224/05572 ,  H01L2224/05611 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/13099 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49135 ,  Y10T29/49139 ,  Y10T29/49144 ,  Y10T29/49155 ,  Y10T29/49158 ,  Y10T29/49222 ,  H01L2924/00 ,  H01L2924/00014

摘要： An electrical connection terminal of an embedded chip and a method for fabricating the same are proposed. Firstly, an insulating layer is provided on a circuit board integrated with a chip and is produced a plurality of first openings on the circuit board, wherein at least one of the first openings corresponds to a position of a conductive pad of the chip to expose the conductive pad. Then, a first metal layer is formed on the conductive pad and a conductive layer is formed on the surface of the first metal layer, insulating layer and the first openings. A patterned resist layer having a plurality of second openings is formed on the conductive layer to expose a part of the conductive layer to be subsequently deposited with a second metal layer, wherein at least one of the second openings of the resist layer is located correspondingly to the conductive pad. Subsequently, the second metal layer is formed on the exposed part of the conductive layer by an electroplating process. By such arrangement, the fabrication of the conductive structure of the conductive pad of the chip and build-up of conductive circuits on the circuit board can be simultaneously integrated to simplify processes and costs of the fabrication.

摘要翻译： 提出了嵌入式芯片的电连接端子及其制造方法。 首先，在与芯片集成的电路板上设置绝缘层，并且在电路板上制造多个第一开口，其中至少一个第一开口对应于芯片的导电焊盘的位置以露出 导电垫。 然后，在导电焊盘上形成第一金属层，在第一金属层，绝缘层和第一开口的表面上形成导电层。 具有多个第二开口的图案化抗蚀剂层形成在导电层上，以暴露出随后沉积有第二金属层的导电层的一部分，其中抗蚀剂层的至少一个第二开口对应于 导电垫。 随后，通过电镀工艺在导电层的暴露部分上形成第二金属层。 通过这种布置，芯片的导电焊盘的导电结构的制造和电路板上的导电电路的积聚可以被同时整合，以简化制造的工艺和成本。

公开(公告)号：US20060226544A1

公开(公告)日：2006-10-12

申请号：US11448420

申请日：2006-06-06

申请人： Shih-Ping Hsu ,  Kun-Chen Tsai

发明人： Shih-Ping Hsu ,  Kun-Chen Tsai

IPC分类号： H01L23/48

CPC分类号： H01L24/02 ,  H01L21/4846 ,  H01L21/486 ,  H01L23/3128 ,  H01L23/498 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/0401 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/1532 ,  H05K1/113 ,  H05K3/108 ,  H05K3/243 ,  H05K3/28 ,  H05K3/423 ,  H05K2201/0394 ,  H05K2201/09563 ,  H05K2203/0574 ,  H01L2924/00015 ,  H01L2224/05599 ,  H01L2924/00

摘要： A semiconductor package substrate and a method for fabricating the same are proposed. An insulating layer has a plurality of blind vias to expose inner traces underneath the insulating layer. A conductive film is formed on the insulating layer and over the bind vias. A first resist is formed on the conductive film, having openings to expose parts of the conductive film. A patterned trace layer including a plurality of contact pads is formed in the openings and the blind vias to form conductive vias, with at least one contact pad electrically connected to one conductive via. A second resist is formed on the patterned trace layer without covering the contact pads. A metal barrier layer is formed on the contact pads. Finally, the first and second resists and parts of the conductive film covered the first resist are removed.

摘要翻译： 提出了半导体封装基板及其制造方法。 绝缘层具有多个盲孔以暴露绝缘层下方的内部迹线。 在绝缘层上和结合通孔上形成导电膜。 第一抗蚀剂形成在导电膜上，具有露出导电膜部分的开口。 在开口和盲孔中形成包括多个接触焊盘的图案化迹线层，以形成导电通路，其中至少一个接触焊盘电连接到一个导电通孔。 在图案化的迹线层上形成第二抗蚀剂而不覆盖接触焊盘。 在接触焊盘上形成金属阻挡层。 最后，去除覆盖第一抗蚀剂的导电膜的第一和第二抗蚀剂和部分。

公开(公告)号：US20060223230A1

公开(公告)日：2006-10-05

申请号：US11424797

申请日：2006-06-16

申请人： Shih-Ping Hsu ,  Kun-Chen Tsai

发明人： Shih-Ping Hsu ,  Kun-Chen Tsai

IPC分类号： H01L21/00

CPC分类号： H01L24/02 ,  H01L21/4846 ,  H01L21/486 ,  H01L23/3128 ,  H01L23/498 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/0401 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/1532 ,  H05K1/113 ,  H05K3/108 ,  H05K3/243 ,  H05K3/28 ,  H05K3/423 ,  H05K2201/0394 ,  H05K2201/09563 ,  H05K2203/0574 ,  H01L2924/00015 ,  H01L2224/05599 ,  H01L2924/00

摘要： A semiconductor package substrate and a method for fabricating the same are proposed. An insulating layer has a plurality of blind vias to expose inner traces underneath the insulating layer. A conductive film is formed on the insulating layer and over the bind vias. A first resist is formed on the conductive film, having openings to expose parts of the conductive film. A patterned trace layer including a plurality of contact pads is formed in the openings and the blind vias to form conductive vias, with at least one contact pad electrically connected to one conductive via. A second resist is formed on the patterned trace layer without covering the contact pads. A metal barrier layer is formed on the contact pads. Finally, the first and second resists and parts of the conductive film covered the first resist are removed.

摘要翻译： 提出了半导体封装基板及其制造方法。 绝缘层具有多个盲孔以暴露绝缘层下方的内部迹线。 在绝缘层上和结合通孔上形成导电膜。 第一抗蚀剂形成在导电膜上，具有露出导电膜部分的开口。 在开口和盲孔中形成包括多个接触焊盘的图案化迹线层，以形成导电通路，其中至少一个接触焊盘电连接到一个导电通孔。 在图案化的迹线层上形成第二抗蚀剂而不覆盖接触焊盘。 在接触焊盘上形成金属阻挡层。 最后，去除覆盖第一抗蚀剂的导电膜的第一和第二抗蚀剂和部分。

公开(公告)号：US20050037601A1

公开(公告)日：2005-02-17

申请号：US10695356

申请日：2003-10-27

申请人： Shih-Ping Hsu ,  Kun-Chen Tsai

发明人： Shih-Ping Hsu ,  Kun-Chen Tsai

IPC分类号： H01L21/60 ,  H01L21/48 ,  H01L23/498 ,  H05K3/10 ,  H05K3/24 ,  H05K3/28 ,  H05K3/42 ,  H01L21/44 ,  H01L21/50

CPC分类号： H01L24/02 ,  H01L21/4846 ,  H01L21/486 ,  H01L23/3128 ,  H01L23/498 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/0401 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/1532 ,  H05K1/113 ,  H05K3/108 ,  H05K3/243 ,  H05K3/28 ,  H05K3/423 ,  H05K2201/0394 ,  H05K2201/09563 ,  H05K2203/0574 ,  H01L2924/00015 ,  H01L2224/05599 ,  H01L2924/00

摘要： A semiconductor package substrate and a method for fabricating the same are proposed. An insulating layer has a plurality of blind vias to expose inner traces underneath the insulating layer. A conductive film is formed on the insulating layer and over the bind vias. A first resist is formed on the conductive film, having openings to expose parts of the conductive film. A patterned trace layer including a plurality of contact pads is formed in the openings and the blind vias to form conductive vias, with at least one contact pad electrically connected to one conductive via. A second resist is formed on the patterned trace layer without covering the contact pads. A metal barrier layer is formed on the contact pads. Finally, the first and second resists and parts of the conductive film covered the first resist are removed.

摘要翻译： 提出了半导体封装基板及其制造方法。 绝缘层具有多个盲孔以暴露绝缘层下方的内部迹线。 在绝缘层上和结合通孔上形成导电膜。 第一抗蚀剂形成在导电膜上，具有露出导电膜部分的开口。 在开口和盲孔中形成包括多个接触焊盘的图案化迹线层，以形成导电通路，其中至少一个接触焊盘电连接到一个导电通孔。 在图案化的迹线层上形成第二抗蚀剂而不覆盖接触焊盘。 在接触焊盘上形成金属阻挡层。 最后，去除覆盖第一抗蚀剂的导电膜的第一和第二抗蚀剂和部分。