公开(公告)号：US20080190899A1

公开(公告)日：2008-08-14

申请号：US11793738

申请日：2005-12-22

申请人： Toshio Sugahara ,  Noritoshi Takasaki ,  Harumi Takasaki ,  Hideo Aoki

发明人： Toshio Sugahara ,  Noritoshi Takasaki ,  Harumi Takasaki ,  Hideo Aoki

IPC分类号： B23K9/32 ,  B23K11/00 ,  B23K11/10

CPC分类号： B23K11/314 ,  B23K11/11 ,  B23K11/3018 ,  B23K11/3072

摘要： An electrode tip holder, a welding method, and an electrode tip adjusting device. The electrode tip holder comprises a chuck body having an inner diameter hole with a first tapered inner peripheral surface diverging toward the tip thereof, a lock nut threaded with the tip male screw part of the chuck body, and a collet fitted to the inner diameter hole. The collet is axially pressed since the lock nut is threaded with the tip male screw part and reduced in diameter by the elastic deformation of a slit to hold an electrode tip fitted to the inside thereof. The chuck body comprises a coolant supply port supplying a coolant to a groove part and a coolant recovery port recovering the coolant from the groove part which are opened at positions facing the groove part.

摘要翻译： 电极头保持器，焊接方法以及电极头调整装置。 电极头保持器包括具有内径孔的卡盘体，内径孔具有朝向其前端分叉的第一锥形内周面，与卡盘主体的前端外螺纹部分螺纹连接的锁紧螺母，以及装配到内径孔 。 夹头被轴向按压，因为锁紧螺母与前端外螺纹部分螺纹连接，并且通过狭缝的弹性变形直径减小，以保持安装在其内部的电极头。 卡盘体包括向槽部供应冷却剂的冷却剂供给口和从凹槽部回收冷却剂的冷却剂回收口，所述冷却剂回收口在面向槽部的位置处开口。

公开(公告)号：US08409919B2

公开(公告)日：2013-04-02

申请号：US12882673

申请日：2010-09-15

申请人： Hideo Aoki ,  Masatoshi Fukuda ,  Kanako Sawada ,  Yasuhiro Koshio

发明人： Hideo Aoki ,  Masatoshi Fukuda ,  Kanako Sawada ,  Yasuhiro Koshio

IPC分类号： H01L21/60

CPC分类号： H01L24/81 ,  H01L24/13 ,  H01L24/16 ,  H01L24/75 ,  H01L2224/75 ,  H01L2224/75251 ,  H01L2224/75252 ,  H01L2224/7592 ,  H01L2224/81065 ,  H01L2224/81093 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81205 ,  H01L2224/81208 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/81907 ,  H01L2224/81986 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/00

摘要： According to a manufacturing method of one embodiment, a first solder bump and a second solder bump are aligned and placed in contact with each other, and thereafter, the first and second solder bumps are heated to a temperature equal or higher than a melting point of the solder bumps and melted, whereby a partially connection body of the first solder bump and the second solder bump is formed. The partially connection body is cooled. The cooled partially connection body is heated to a temperature equal to or higher than the melting point of the solder bump in a reducing atmosphere, thereby to form a permanent connection body by melting the partially connection body while removing an oxide film existing on a surface of the partially connection body.

摘要翻译： 根据一个实施例的制造方法，将第一焊料凸块和第二焊料凸块对齐并且彼此接触放置，然后将第一和第二焊料凸块加热至等于或高于 焊料凸起并熔化，由此形成第一焊料凸块和第二焊料凸块的部分连接体。 部分连接体被冷却。 冷却的部分连接体在还原气氛中被加热到等于或高于焊料凸点的熔点的温度，从而通过熔化部分连接体而形成永久性连接体，同时除去存在于表面上的氧化膜 部分连接体。

公开(公告)号：US08093723B2

公开(公告)日：2012-01-10

申请号：US13098648

申请日：2011-05-02

申请人： Takako Funakoshi ,  Eiichi Murakami ,  Kazumasa Yanagisawa ,  Kan Takeuchi ,  Hideo Aoki ,  Hizuru Yamaguchi ,  Takayuki Oshima ,  Kazuyuki Tsunokuni ,  Kousuke Okuyama

发明人： Takako Funakoshi ,  Eiichi Murakami ,  Kazumasa Yanagisawa ,  Kan Takeuchi ,  Hideo Aoki ,  Hizuru Yamaguchi ,  Takayuki Oshima ,  Kazuyuki Tsunokuni ,  Kousuke Okuyama

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L23/53238 ,  H01L21/823871 ,  H01L23/5286 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a semiconductor integrated circuit device having plural layers of buried wirings, it is intended to prevent the occurrence of a discontinuity caused by stress migration at an interface between a plug connected at a bottom thereof to a buried wiring and the buried wiring. For example, in the case where the width of a first Cu wiring is not smaller than about 0.9 μm and is smaller than about 1.44 μm, and the width of a second Cu wiring and the diameter of a plug are about 0.18 μm, there are arranged two or more plugs which connect the first wirings and the second Cu wirings electrically with each other.

摘要翻译： 在具有多层埋地布线的半导体集成电路器件中，旨在防止在其底部连接到埋地布线的插头与埋地布线之间的界面处的应力迁移引起的不连续性的发生。 例如，在第一Cu布线的宽度不小于约0.9μm且小于约1.44μm的情况下，并且第二Cu布线的宽度和塞子的直径为约0.18μm的情况下，存在 布置两个或更多个将第一布线和第二铜布线彼此电连接的插头。

公开(公告)号：US20110298873A1

公开(公告)日：2011-12-08

申请号：US13210794

申请日：2011-08-16

申请人： Goro KATSUYAMA ,  Masaaki Kabumoto ,  Kanae Amemiya ,  Osamu Miki ,  Hideo Aoki ,  Akiyoshi Tanaka

发明人： Goro KATSUYAMA ,  Masaaki Kabumoto ,  Kanae Amemiya ,  Osamu Miki ,  Hideo Aoki ,  Akiyoshi Tanaka

IPC分类号： B41J2/175

CPC分类号： B41J2/17509 ,  B41J2/1752 ,  B41J2/1755 ,  B41J2/17553 ,  B41J13/106 ,  B41J29/13

摘要： An image forming apparatus is disclosed that includes a substantially flat top face and a slanted front face, the bottom side of which recedes backward. The image forming apparatus may includes a paper discharge tray disposed at a lower portion of the slanted front face, the paper discharge tray protruding forward. The paper discharge tray may be tiltable upward and downward. Because the bottom side of the slanted front face recedes backward, the flat top face can be provided, and simultaneously, enough space for the feeding and discharging of paper can be secured.

摘要翻译： 公开了一种图像形成装置，其包括基本平坦的顶面和倾斜的前表面，其底侧向后退。 图像形成装置可以包括设置在倾斜前表面的下部的排纸盘，排纸盘向前突出。 排纸托盘可以向上和向下倾斜。 因为倾斜的前面的底侧向后退，所以可以设置平坦的顶面，同时可以确保足够的空间用于纸张的进给和排出。

公开(公告)号：US07877871B2

公开(公告)日：2011-02-01

申请号：US12230280

申请日：2008-08-27

申请人： Hideo Aoki ,  Naoko Yamaguchi ,  Chiaki Takubo ,  Toshiaki Yamauchi ,  Koji Imamiya ,  Hiroshi Hashizume

发明人： Hideo Aoki ,  Naoko Yamaguchi ,  Chiaki Takubo ,  Toshiaki Yamauchi ,  Koji Imamiya ,  Hiroshi Hashizume

IPC分类号： H05K3/02 ,  G03G15/16

CPC分类号： H05K3/207 ,  G03G15/6591 ,  G03G2215/00523 ,  H05K1/095 ,  H05K3/1266 ,  H05K3/246 ,  H05K2201/0347 ,  H05K2201/09781 ,  H05K2203/0517 ,  H05K2203/105 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49165

摘要： An image forming apparatus comprises an exposure unit forming an electrostatic latent image on a photo conductor based on image information, a developing unit developing the electrostatic latent image by toner made of formation material of a circuitry layer, and an electrostatic transferring unit transferring a toner image on the photo conductor onto a substrate. The toner image is transferred so as to cover at least a part of a conductor layer formed on the substrate. At this time, excessive charges caused in the conductor layer accompanying the start of the transfer of the toner image are removed. Alternatively, charges of which polarity is reverse to that of the toner are added to the conductor layer. These allow the circuitry layer to be formed to have a desired pattern favorably and securely on the conductor layer.

摘要翻译： 图像形成装置包括基于图像信息在光导体上形成静电潜像的曝光单元，通过电路层的形成材料制成的调色剂来显影静电潜像的显影单元和传送调色剂图像的静电转印单元 在光导体上的基片上。 转印调色剂图像以覆盖形成在基板上的导体层的至少一部分。 此时，伴随着调色剂图像的转印开始导致的导体层中引起的过多的电荷被去除。 或者，将与该调色剂相反极性的电荷加到导体层中。 这些允许电路层形成为在导体层上有利地并且牢固地具有期望的图案。

公开(公告)号：US20100000083A1

公开(公告)日：2010-01-07

申请号：US12541568

申请日：2009-08-14

申请人： Naoko Yamaguchi ,  Hideo Aoki ,  Chiaki Takubo

发明人： Naoko Yamaguchi ,  Hideo Aoki ,  Chiaki Takubo

IPC分类号： H05K3/10 ,  H05K3/20

CPC分类号： H05K3/246 ,  G03G15/6585 ,  H01L23/49883 ,  H01L2924/0002 ,  H05K1/095 ,  H05K3/1266 ,  H05K3/4664 ,  H05K2201/0212 ,  H05K2201/0347 ,  H05K2203/0517 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49158 ,  Y10T29/4916 ,  Y10T428/12097 ,  Y10T428/12104 ,  Y10T428/12111 ,  Y10T428/24917 ,  H01L2924/00

摘要： According to one mode of the present invention, metal-containing resin particles comprising a resin containing a thermosetting resin at 50 wt % or more and having a rate of moisture absorption from 500 to 14500 ppm, and fine metal particles contained in the resin, is provided.

摘要翻译： 根据本发明的一种模式，含有含有50重量％以上的热固性树脂的树脂含水率为500〜14500ppm的含金属的树脂粒子和树脂中含有的微细金属粒子是 提供。

公开(公告)号：US07411301B2

公开(公告)日：2008-08-12

申请号：US11239371

申请日：2005-09-30

申请人： Takako Funakoshi ,  Eiichi Murakami ,  Kazumasa Yanagisawa ,  Kan Takeuchi ,  Hideo Aoki ,  Hizuru Yamaguchi ,  Takayuki Oshima ,  Kazuyuki Tsunokuni ,  Kousuke Okuyama

发明人： Takako Funakoshi ,  Eiichi Murakami ,  Kazumasa Yanagisawa ,  Kan Takeuchi ,  Hideo Aoki ,  Hizuru Yamaguchi ,  Takayuki Oshima ,  Kazuyuki Tsunokuni ,  Kousuke Okuyama

IPC分类号： H01L23/48 ,  H01L23/52

CPC分类号： H01L23/53238 ,  H01L21/823871 ,  H01L23/5286 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a semiconductor integrated circuit device having plural layers of buried wirings, it is intended to prevent the occurrence of a discontinuity caused by stress migration at an interface between a plug connected at a bottom thereof to a buried wiring and the buried wiring. For example, in the case where the width of a first Cu wiring is not smaller than about 0.9 μm and is smaller than about 1.44 μm, and the width of a second Cu wiring and the diameter of a plug are about 0.18 μm, there are arranged two or more plugs which connect the first wirings and the second Cu wirings electrically with each other.

摘要翻译： 在具有多层埋地布线的半导体集成电路器件中，旨在防止在其底部连接到埋地布线的插头与埋地布线之间的界面处的应力迁移引起的不连续性的发生。 例如，在第一Cu布线的宽度不小于约0.9μm且小于约1.44μm的情况下，并且第二Cu布线的宽度和塞子的直径为约0.18μm的情况下，存在 布置两个或更多个将第一布线和第二铜布线彼此电连接的插头。

公开(公告)号：US07282434B2

公开(公告)日：2007-10-16

申请号：US11485976

申请日：2006-07-14

申请人： Tsuyoshi Tamaru ,  Kazutoshi Oomori ,  Noriko Miura ,  Hideo Aoki ,  Takayuki Oshima

发明人： Tsuyoshi Tamaru ,  Kazutoshi Oomori ,  Noriko Miura ,  Hideo Aoki ,  Takayuki Oshima

IPC分类号： H01L21/4763

CPC分类号： H01L21/76834 ,  H01L21/02131 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/02167 ,  H01L21/022 ,  H01L21/02203 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/3144 ,  H01L21/3145 ,  H01L21/3148 ,  H01L21/31608 ,  H01L21/31629 ,  H01L21/3185 ,  H01L21/76801 ,  H01L21/76811 ,  H01L21/76829 ,  H01L21/76832 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of manufacturing a semiconductor integrated circuit device is provided including forming a first insulating film comprised of fluorine-containing silicon oxide over a main surface of a semiconductor substrate is formed together with forming a second insulating film comprising silicon oxide as a major component, forming a third insulating film comprising silicon carbide as a major component, and forming a fourth insulating film comprised of fluorine-containing silicon oxide. The fourth insulating film is removed at a wiring groove-forming region thereof by dry etching using a first photoresist film as a mask. A first conductive layer is buried inside the wiring groove and the first conductive layer is removed from outside of the wiring groove by a chemical mechanical polishing method, thereby forming a first wiring including the first conductive layer inside the wiring groove.

摘要翻译： 提供一种制造半导体集成电路器件的方法，包括在半导体衬底的主表面上形成由含氟氧化硅构成的第一绝缘膜，同时形成包含氧化硅作为主要成分的第二绝缘膜，形成 以碳化硅为主要成分的第三绝缘膜，形成由含氟氧化硅构成的第四绝缘膜。 通过使用第一光致抗蚀剂膜作为掩模的干蚀刻在其布线槽形成区域处去除第四绝缘膜。 第一导电层被埋在布线槽内部，并且通过化学机械抛光方法从布线槽的外部去除第一导电层，从而在布线槽内形成包括第一导电层的第一布线。

公开(公告)号：US20060071271A1

公开(公告)日：2006-04-06

申请号：US11230624

申请日：2005-09-21

申请人： Ichiro Omura ,  Kenji Takahashi ,  Chiaki Takubo ,  Hideo Aoki ,  Hideo Numata ,  Mie Matsuo ,  Hirokazu Ezawa ,  Susumu Harada ,  Hisashi Kaneko ,  Hiroshi Ikenoue ,  Kenichi Matsushita

发明人： Ichiro Omura ,  Kenji Takahashi ,  Chiaki Takubo ,  Hideo Aoki ,  Hideo Numata ,  Mie Matsuo ,  Hirokazu Ezawa ,  Susumu Harada ,  Hisashi Kaneko ,  Hiroshi Ikenoue ,  Kenichi Matsushita

IPC分类号： H01L29/76 ,  H01L21/336

CPC分类号： H01L29/41766 ,  H01L23/481 ,  H01L24/14 ,  H01L24/17 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L29/7809 ,  H01L29/7811 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05568 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48472 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/00012 ,  H01L2224/05005 ,  H01L2224/05541 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor device which is compact and thin in size, low in resistance of a current path and parasitic inductance and excellent in reliability is provided. This semiconductor device comprises a semiconductor substrate, a first main electrode which is formed on a front surface of the semiconductor substrate, a second main electrode which is formed on a rear surface of the semiconductor substrate, and a conducting portion which is formed in a direction to pierce through the semiconductor substrate, wherein the second main electrode is extracted to the front surface of the semiconductor substrate via the conducting portion. And, the conducting portion is a through via which has a through hole formed through the semiconductor substrate in its thickness direction and a conductive portion which is formed in the through hole and connected to the second main electrode.

摘要翻译： 提供了一种尺寸小型化，电流通路电阻低，寄生电感小，可靠性优异的半导体装置。 该半导体器件包括半导体衬底，形成在半导体衬底的前表面上的第一主电极，形成在半导体衬底的后表面上的第二主电极和形成在半导体衬底的背面上的导电部分 穿过半导体衬底，其中第二主电极经由导电部分被提取到半导体衬底的前表面。 并且，导电部是贯通通孔，该通孔在其厚度方向上形成有通过半导体基板的通孔，以及形成在通孔中并连接到第二主电极的导电部。

公开(公告)号：US07023091B2

公开(公告)日：2006-04-04

申请号：US10465541

申请日：2003-06-20

申请人： Takako Funakoshi ,  Eiichi Murakami ,  Kazumasa Yanagisawa ,  Kan Takeuchi ,  Hideo Aoki ,  Hizuru Yamaguchi ,  Takayuki Oshima ,  Kazuyuki Tsunokuni

发明人： Takako Funakoshi ,  Eiichi Murakami ,  Kazumasa Yanagisawa ,  Kan Takeuchi ,  Hideo Aoki ,  Hizuru Yamaguchi ,  Takayuki Oshima ,  Kazuyuki Tsunokuni

IPC分类号： H01L23/48 ,  H01L23/52

CPC分类号： H01L23/53238 ,  H01L21/823871 ,  H01L23/5286 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a semiconductor integrated circuit device having plural layers of buried wirings, it is intended to prevent the occurrence of a discontinuity caused by stress migration at an interface between a plug connected at a bottom thereof to a buried wiring and the buried wiring. For example, in the case where the width of a first Cu wiring is not smaller than about 0.9 μm and is smaller than about 1.44 μm, and the width of a second Cu wiring and the diameter of a plug are about 0.18 μm, there are arranged two or more plugs which connect the first wirings and the second Cu wirings electrically with each other.

摘要翻译： 在具有多层埋地布线的半导体集成电路器件中，旨在防止在其底部连接到埋地布线的插头与埋地布线之间的界面处的应力迁移引起的不连续性的发生。 例如，在第一Cu布线的宽度不小于约0.9μm且小于约1.44μm的情况下，并且第二Cu布线的宽度和塞子的直径为约0.18μm的情况下，存在 布置两个或更多个将第一布线和第二铜布线彼此电连接的插头。