摘要:
Disclosed is a method of forming an integrated circuit structure that forms lead-free connectors on a device, surrounds the lead-free connectors with a compressible film, connects the device to a carrier (the lead-free connectors electrically connect the device to the carrier), and fills the gaps between the carrier and the device with an insulating underfill.
摘要:
Disclosed is a method of forming an integrated circuit structure that forms lead-free connectors on a device, surrounds the lead-free connectors with a compressible film, connects the device to a carrier (the lead-free connectors electrically connect the device to the carrier), and fills the gaps between the carrier and the device with an insulating underfill.
摘要:
Disclosed is a laminated (or non-laminated) conductive interconnection for joining an integrated circuit device to a device carrier, where the conductive interconnection comprises alternating metal layers and polymer layers. In addition, the polymer can include dendrites, metal projections from the carrier or device, and/or micelle brushes on the outer portion of the polymer. The polymer layers include metal particles and the alternating metal layers and polymer layers form either a cube-shaped structure or a cylinder-shaped structure.
摘要:
Disclosed is a laminated (or non-laminated) conductive interconnection for joining an integrated circuit device to a device carrier, where the conductive interconnection comprises alternating metal layers and polymer layers. In addition, the polymer can include dendrites, metal projections from the carrier or device, and/or micelle brushes on the outer portion of the polymer. The polymer layers include metal particles and the alternating metal layers and polymer layers form either a cube-shaped structure or a cylinder-shaped structure.
摘要:
A method of forming compliant electrical contacts includes patterning a conductive layer into an array of compliant members. The array of compliant members is then positioned to be in contact with electrical connection pads on an integrated circuit wafer and the compliant members are joined to the pads. Then, the supporting layer that supported the compliant members is removed to leave the compliant members connected to the pads.
摘要:
A method for forming interconnects onto attachment points of a wafer includes the steps of providing a mold with a plurality of cavities having a predetermined shape, depositing a release agent on surfaces of the cavities, filling the cavities with an interconnect material to form the interconnects, removing the release agent from the mold, and attaching the interconnects to the attachment points of the wafer. An adhesive layer can optionally be deposited in addition to the release layer. The adhesive layer can be used, for example, to bond the chip to a package.
摘要:
A method for forming interconnects onto attachment points of a wafer includes the steps of providing a mold with a plurality of cavities having a predetermined shape, depositing a release agent on surfaces of the cavities, filling the cavities with an interconnect material to form the interconnects, removing the release agent from the mold, and attaching the interconnects to the attachment points of the wafer. An adhesive layer can optionally be deposited in addition to the release layer. The adhesive layer can be used, for example, to bond the chip to a package.
摘要:
A method for forming interconnects onto attachment points of a wafer includes the steps of providing a mold with a plurality of cavities having a predetermined shape, depositing a release agent on surfaces of the cavities, filling the cavities with an interconnect material to form the interconnects, removing the release agent from the mold, and attaching the interconnects to the attachment points of the wafer. An adhesive layer can optionally be deposited in addition to the release layer. The adhesive layer can be used, for example, to bond the chip to a package.
摘要:
Under the present invention, a semiconductor chip is electrically connected to a substrate (e.g., organic, ceramic, etc.) by an interposer structure. The interposer structure comprises an elastomeric, compliant material that includes metallurgic through connections having a predetermined shape. In a typical embodiment, the metallurgical through connections electrically connect an under bump metallization of the semiconductor chip to a top surface metallization of the substrate. By utilizing the interposer structure in accordance with the present invention, the problems associated with previous semiconductor module designs are alleviated.
摘要:
A microelectronic element and a related method for fabricating such is provided. The microelectronic element comprises a contact pad overlying a major surface of a substrate. The contact pad has a composition including copper at a contact surface. A passivation layer is also provided overlying the major surface of the substrate. The passivation layer overlies the contact pad such that it exposes at least a portion of the contact surface. A plurality of metal layers arranged in a stack overlie the contact surface and at least a portion of the passivation layer. The stack includes multiple layers, which can have different thicknesses and different metals, with the lowest layer including titanium (Ti) and nickel (Ni) in contact with the contact surface.