公开(公告)号：US09508563B2

公开(公告)日：2016-11-29

申请号：US13548029

申请日：2012-07-12

申请人： Woon-Seong Kwon ,  Suresh Ramalingam

发明人： Woon-Seong Kwon ,  Suresh Ramalingam

IPC分类号： H01L21/48 ,  H01L23/14 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065

CPC分类号： H01L21/4853 ,  H01L23/147 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/75 ,  H01L24/81 ,  H01L24/97 ,  H01L25/0655 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/75744 ,  H01L2224/7598 ,  H01L2224/75983 ,  H01L2224/75987 ,  H01L2224/81005 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/3511 ,  H01L2924/014 ,  H01L2224/16225 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/81 ,  H01L2924/00014

摘要： A method for flip chip stacking includes forming a cavity wafer comprising a plurality of cavities and a pair of corner guides, placing a through-silicon-via (TSV) interposer with solder bumps coupled to a surface of the TSV interposer on the cavity wafer, such that the solder bumps are situated in the plurality of cavities and the TSV interposer is situated between the pair of corner guides, placing an integrated circuit (IC) die on another surface of the TSV interposer, such that the IC die, the TSV interposer, and the solder bumps form a stacked interposer unit, removing the stacked interposer unit from the cavity wafer, and bonding the solder bumps of the stacked interposer unit to an organic substrate such that the stacked interposer unit and the organic substrate form a flip chip.

摘要翻译： 一种用于倒装芯片堆叠的方法包括：形成包括多个空腔的空腔晶片和一对角引导件，将具有耦合到腔晶片上的TSV插入器表面的焊料凸块放置穿通硅通孔（TSV）插入器， 使得焊料凸块位于多个空腔中，并且TSV插入件位于一对拐角引导件之间，将集成电路（IC）管芯放置在TSV插入器的另一表面上，使得IC管芯，TSV插入器 并且焊料凸起形成堆叠的插入单元，从空腔晶片去除堆叠的中介层单元，并且将堆叠的插入单元的焊料凸块接合到有机基板，使得堆叠的插入单元和有机基板形成倒装芯片。

公开(公告)号：US08618648B1

公开(公告)日：2013-12-31

申请号：US13548041

申请日：2012-07-12

申请人： Woon-Seong Kwon ,  Suresh Ramalingam

发明人： Woon-Seong Kwon ,  Suresh Ramalingam

IPC分类号： H01L23/02 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/00

CPC分类号： H01L24/75 ,  H01L23/147 ,  H01L23/49827 ,  H01L24/81 ,  H01L24/97 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16235 ,  H01L2224/75724 ,  H01L2224/75983 ,  H01L2224/81815 ,  H01L2224/95 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2924/014

摘要： A cavity wafer for flip chip stacking includes an electrostatic (ESC) chuck wafer with a plurality of cavities, and a bonding layer on a surface of the ESC chuck wafer. The bonding layer is configured to receive a through-silicon-via (TSV) interposer with solder bumps. The plurality of cavities are configured to receive the solder bumps at the TSV interposer. The bonding layer is configured to receive an electrostatic bias for bonding the ESC chuck wafer to the TSV interposer with the solder bumps.

摘要翻译： 用于倒装芯片堆叠的空腔晶片包括具有多个空腔的静电（ESC）卡盘晶片和ESC卡盘晶片的表面上的结合层。 接合层被配置为接收具有焊料凸块的穿硅通孔（TSV）插入器。 多个空腔被配置为在TSV插入器处接收焊料凸块。 接合层被配置为接收用于将ESC卡盘晶片与焊料凸块接合到TSV插入件的静电偏压。

公开(公告)号：US20140017852A1

公开(公告)日：2014-01-16

申请号：US13548029

申请日：2012-07-12

申请人： Woon-Seong Kwon ,  Suresh Ramalingam

发明人： Woon-Seong Kwon ,  Suresh Ramalingam

IPC分类号： H01L21/98

CPC分类号： H01L21/4853 ,  H01L23/147 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/75 ,  H01L24/81 ,  H01L24/97 ,  H01L25/0655 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/75744 ,  H01L2224/7598 ,  H01L2224/75983 ,  H01L2224/75987 ,  H01L2224/81005 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/3511 ,  H01L2924/014 ,  H01L2224/16225 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/81 ,  H01L2924/00014

摘要： A method for flip chip stacking includes forming a cavity wafer comprising a plurality of cavities and a pair of corner guides, placing a through-silicon-via (TSV) interposer with solder bumps coupled to a surface of the TSV interposer on the cavity wafer, such that the solder bumps are situated in the plurality of cavities and the TSV interposer is situated between the pair of corner guides, placing an integrated circuit (IC) die on another surface of the TSV interposer, such that the IC die, the TSV interposer, and the solder bumps form a stacked interposer unit, removing the stacked interposer unit from the cavity wafer, and bonding the solder bumps of the stacked interposer unit to an organic substrate such that the stacked interposer unit and the organic substrate form a flip chip.

摘要翻译： 一种用于倒装芯片堆叠的方法包括：形成包括多个空腔的空腔晶片和一对角引导件，将具有耦合到腔晶片上的TSV插入器表面的焊料凸块放置穿通硅通孔（TSV）插入器， 使得焊料凸块位于多个空腔中，并且TSV插入件位于一对拐角引导件之间，将集成电路（IC）管芯放置在TSV插入器的另一表面上，使得IC管芯，TSV插入器 并且焊料凸起形成堆叠的插入单元，从空腔晶片去除堆叠的中介层单元，并且将堆叠的插入单元的焊料凸块接合到有机基板，使得堆叠的插入单元和有机基板形成倒装芯片。

公开(公告)号：US09236341B1

公开(公告)日：2016-01-12

申请号：US12868529

申请日：2010-08-25

申请人： Dong W. Kim ,  Myung-June Lee ,  Suresh Ramalingam

发明人： Dong W. Kim ,  Myung-June Lee ,  Suresh Ramalingam

IPC分类号： H01L23/58 ,  H01L23/522

CPC分类号： H01L23/5226 ,  H01L21/486 ,  H01L21/76898 ,  H01L23/147 ,  H01L23/49827 ,  H01L2224/16225 ,  H01L2924/15311

摘要： A silicon interposer includes a plurality of patterned metal layers formed on a silicon wafer portion and a plurality of through-silicon vias extending through the silicon wafer portion. The through-silicon vias have an interdiffusion conductive element.

摘要翻译： 硅插入件包括形成在硅晶片部分上的多个图案化金属层和延伸穿过硅晶片部分的多个穿硅通孔。 穿硅通孔具有相互扩散的导电元件。

公开(公告)号：USRE44629E1

公开(公告)日：2013-12-10

申请号：US11001714

申请日：2004-11-30

申请人： Suresh Ramalingam ,  Nagesh Vodrahalli ,  Michael J. Costello ,  Mun Leong Loke ,  Ravi V. Mahajan

发明人： Suresh Ramalingam ,  Nagesh Vodrahalli ,  Michael J. Costello ,  Mun Leong Loke ,  Ravi V. Mahajan

IPC分类号： H01K3/10

CPC分类号： H01L21/563 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/01077 ,  H01L2924/15151 ,  H01L2924/15311 ,  Y10T29/4913 ,  Y10T29/49146 ,  Y10T29/49163 ,  Y10T29/49165 ,  H01L2924/00 ,  H01L2224/0401

摘要： The present invention involves a method of providing an integrated circuit package having a substrate with a vent opening. The integrated circuit package includes a substrate having an opening and an integrated circuit mounted to the substrate. An underfill material is dispensed between the substrate and the integrated circuit.

摘要翻译： 本发明涉及一种提供集成电路封装的方法，所述集成电路封装具有带通气孔的基板。 集成电路封装包括具有开口的基板和安装到基板的集成电路。 在基板和集成电路之间分配底部填充材料。

公开(公告)号：US06490166B1

公开(公告)日：2002-12-03

申请号：US09330373

申请日：1999-06-11

申请人： Suresh Ramalingam ,  Nagesh Vodrahalli ,  Michael J. Costello ,  Mun Leong Loke ,  Ravi V. Mahajan

发明人： Suresh Ramalingam ,  Nagesh Vodrahalli ,  Michael J. Costello ,  Mun Leong Loke ,  Ravi V. Mahajan

IPC分类号： H01L2100

CPC分类号： H01L21/563 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/01077 ,  H01L2924/15151 ,  H01L2924/15311 ,  Y10T29/4913 ,  Y10T29/49146 ,  Y10T29/49163 ,  Y10T29/49165 ,  H01L2924/00 ,  H01L2224/0401

摘要： The present invention involves a method of providing an integrated circuit package having a substrate with a vent opening. The integrated circuit package includes a substrate having an opening and an integrated circuit mounted to the substrate. An underfill material is dispensed between the substrate and the integrated circuit.

摘要翻译： 本发明涉及一种提供集成电路封装的方法，所述集成电路封装具有带通气孔的基板。 集成电路封装包括具有开口的基板和安装到基板的集成电路。 在基板和集成电路之间分配底部填充材料。

公开(公告)号：US06486440B1

公开(公告)日：2002-11-26

申请号：US09901474

申请日：2001-07-09

申请人： Douglas E. Crafts ,  James F. Farrell ,  Mark B. Farrelly ,  Suresh Ramalingam

发明人： Douglas E. Crafts ,  James F. Farrell ,  Mark B. Farrelly ,  Suresh Ramalingam

IPC分类号： H05B100

CPC分类号： G02B6/30 ,  G02B6/1203 ,  G02B6/36

摘要： A redundant package for optical components includes an inner package enclosing the optical component, and an outer package enclosing the inner package. A heater may be disposed in the inner package proximate the optical component to control its temperature, and to maintain this temperature control, the outer package creates an isolated air pocket around the inner package which thermally insulates the inner package from the outside environment. The outer package is formed of a material having low thermal conductivity, to promote this insulating function. This package is especially useful if the optical component comprises a planar lightwave circuit (PLC), e.g., an arrayed waveguide grating (AWG), which requires tight temperature control and structural integrity to maintain the integrity of the optical paths.

摘要翻译： 用于光学部件的冗余封装包括封装光学部件的内部封装以及封装内部封装的外部封装。 加热器可以靠近光学部件设置在内部包装件中以控制其温度，并且为了保持该温度控制，外部包装围绕内部包装形成隔离的空气袋，其将内部包装与外部环境绝热。 外包装由具有低导热性的材料形成，以促进该绝缘功能。 如果光学组件包括平面光波电路（PLC），例如阵列波导光栅（AWG），则该封装是特别有用的，其需要严格的温度控制和结构完整性来维持光路的完整性。

公开(公告)号：US20130181360A1

公开(公告)日：2013-07-18

申请号：US13353299

申请日：2012-01-18

申请人： Namhoon Kim ,  Joong-Ho Kim ,  Paul Y. Wu ,  Suresh Ramalingam

发明人： Namhoon Kim ,  Joong-Ho Kim ,  Paul Y. Wu ,  Suresh Ramalingam

IPC分类号： H01L23/522 ,  H01L21/50

CPC分类号： H05K3/3436 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/15788 ,  H01L2924/18161 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/147 ,  H05K2201/10189 ,  H05K2201/10378 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2924/00012

摘要： An integrated circuit (IC) structure can include an internal element and a flexible circuitry directly coupled to the internal element. The flexible circuitry can be configured to exchange signals between the internal element and a node external to the IC structure.

摘要翻译： 集成电路（IC）结构可以包括直接耦合到内部元件的内部元件和柔性电路。 柔性电路可以被配置为在内部元件和IC结构外部的节点之间交换信号。

公开(公告)号：US06697553B2

公开(公告)日：2004-02-24

申请号：US10077581

申请日：2002-02-15

申请人： Jyoti Kiron Bhardwaj ,  Robert James Brainard ,  David J. Chapman ,  Douglas E. Crafts ,  Zi-Wen Dong ,  David Dougherty ,  Erik W. Egan ,  James F. Farrell ,  Mark B. Farrelly ,  Niranjan Gopinathan ,  Kenzo Ishida ,  David K. Nakamoto ,  Thomas Thuan Nguyen ,  Suresh Ramalingam ,  Steven M. Swain ,  Sanjay M. Thekdi ,  Anantharaman Vaidyanathan ,  Hiroaki Yamada ,  Yingchao Yan

发明人： Jyoti Kiron Bhardwaj ,  Robert James Brainard ,  David J. Chapman ,  Douglas E. Crafts ,  Zi-Wen Dong ,  David Dougherty ,  Erik W. Egan ,  James F. Farrell ,  Mark B. Farrelly ,  Niranjan Gopinathan ,  Kenzo Ishida ,  David K. Nakamoto ,  Thomas Thuan Nguyen ,  Suresh Ramalingam ,  Steven M. Swain ,  Sanjay M. Thekdi ,  Anantharaman Vaidyanathan ,  Hiroaki Yamada ,  Yingchao Yan

IPC分类号： G02B634

CPC分类号： G02B6/12011 ,  G02B6/105 ,  G02B6/12 ,  G02B6/12016 ,  G02B6/12021 ,  G02B6/12026

摘要： A planar lightwave circuit includes an arrayed waveguide grating (AWG), with input and output waveguides, partially curved array waveguides with respective length differences, and planar waveguide regions for focusing optical energy between the input/output and array waveguides. Optimal waveguide widths and spacing along the planar waveguide region facets are disclosed, which are largely determinative of AWG size and optical performance. Also disclosed are optimal cross-sectional waveguide dimensions (e.g., width and height); modified index of refraction difference between the waveguide core and cladding regions; and optimal array waveguide lengths, path length differences, and free spectral range. These features, especially when combined with advanced fiber attachment, passivation and packaging techniques, result in high-yield, high-performance AWGs (both gaussian and flattop versions).

摘要翻译： 平面光波电路包括阵列波导光栅（AWG），其具有输入和输出波导，具有相应长度差的部分弯曲阵列波导和用于在输入/输出和阵列波导之间聚焦光能的平面波导区域。 公开了沿着平面波导区域面的最佳波导宽度和间距，其主要决定于AWG尺寸和光学性能。 还公开了最佳横截面波导尺寸（例如，宽度和高度）; 波导芯和包层区之间的折射率差异; 和最佳阵列波导长度，路径长度差和自由光谱范围。 这些特性，特别是结合先进的光纤附着，钝化和封装技术，可以获得高产出，高性能的AWG（高斯型和平板型）。

公开(公告)号：US06331446B1

公开(公告)日：2001-12-18

申请号：US09261648

申请日：1999-03-03

申请人： Duane Cook ,  Venkatesan Murali ,  Suresh Ramalingam ,  Nagesh Vodrahalli

发明人： Duane Cook ,  Venkatesan Murali ,  Suresh Ramalingam ,  Nagesh Vodrahalli

IPC分类号： H01L2144

CPC分类号： H01L24/31 ,  H01L21/563 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/83951 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2224/0401

摘要： A partial gel step in the underfilling of an integrated circuit that is mounted to a substrate. The process involves dispensing a first underfill material and then heating the underfill material to a partial gel state. The partial gel step may reduce void formation and improve adhesion performance during moisture loading.

摘要翻译： 在安装到基板上的集成电路的底部填充中的部分凝胶步骤。 该方法包括分配第一底部填充材料，然后将底部填充材料加热至部分凝胶状态。 部分凝胶步骤可以减少空隙形成并改善湿气加载期间的粘附性能。