摘要:
A fiber optical end connector is disclosed, comprising a grooved base member having mounted thereupon a grooved silicon block, and means for holding optical fibers in the grooves on the base member and on the silicon block.
摘要:
An m-input/n-output (e.g., 2.times.2) optical fiber switch is disclosed which alters the location of the fibers by the application of an external force. Illustratively, the switch uses a housing with a diamond-shaped opening extending therethrough, with pairs of optical fibers positioned in orthogonally located V-grooves. Upon the application of an external force, the fibers are moved into the remaining, vacant V-grooves formed by the diamond-shaped opening. In a preferred embodiment, a (2.times.2) switch is magnetically activated.
摘要:
An optical fiber connector pair is provided, which includes a plug assembly and a receptacle. An optical connection can be repeatedly made and broken by insertion and withdrawal, repectively, of the plug assembly relative to the receptacle. The final alignment of the mating fiber ends is provided by a pair of silicon blocks, each having a guiding groove formed in one surface. One block is included in the receptacle, and the other block is included in the plug assembly. One fiber end is affixed in each groove. The act of inserting the plug assembly in the receptacle brings the grooved surfaces together such that each fiber is captured by the opposing groove.
摘要:
The specification describes an integrated passive device (IPD) that is formed on a polysilicon substrate. A method for making the IPD is disclosed wherein the polysilicon substrate is produced starting with a single crystal handle wafer, depositing a thick substrate layer of polysilicon on one or both sides of the starting wafer, forming the IPD on one of the polysilicon substrate layers, and removing the handle wafer. In a preferred embodiment the single crystal silicon handle wafer is a silicon wafer rejected from a single crystal silicon wafer production line.
摘要:
A flexible membrane test apparatus and test method for high-speed IC chips. The method and apparatus rely on locating the reference components of the test circuit very close to the contact pads of the IC chip under test. This is achieved in one embodiment by locating those components adjacent to the flexible membrane. In another embodiment, the reference components may be attached to the membrane itself, so the length of the runners connecting the contact points of the tester and the critical reference components is optimally reduced. In yet a further embodiment, the entire test circuit, in the form of an IC test chip, is located on the membrane.
摘要:
The specification describes an integrated passive device (IPD) that is formed on a polysilicon substrate. A method for making the IPD is disclosed wherein the polysilicon substrate is produced starting with a single crystal handle wafer, depositing a thick substrate layer of polysilicon on one or both sides of the starting wafer, forming the IPD on one of the polysilicon substrate layers, and removing the handle wafer. In a preferred embodiment the single crystal silicon handle wafer is a silicon wafer rejected from a single crystal silicon wafer production line.
摘要:
The specification describes methods for manufacturing thin tiles for IC packages using thinning techniques. The method includes the step of thinning the IC devices in chip form. This is achieved at the final stage of assembly where the chips are flip-chip bonded to the substrate and the backside of the chips is exposed for thinning. Using this approach, final chip thickness of the order of 2-8 mils can be produced and overall package thickness is dramatically reduced.
摘要:
A technique for enabling sufficient flow of flux cleaning fluids and an underfill material in the relatively low-profile gap between a flip-chip bonded IC chip and a substrate, such as a printed circuit board, is to provide at least one aperture in the substrate under the IC chip. The use of such an aperture enables, for example, flux cleaning fluid to flow through the aperture into the low-profile gap between the IC chip and the substrate surface, such as by the application of pressure or by gravity, which then exits through openings between formed interconnect bonds at a sufficient flow rate to adequately remove flux residues. An epoxy underfill to the IC chip can be formed in a similar manner. For example, a relatively thick bead of epoxy, such as on the order of the thickness of the IC chip, is deposited or stencil printed on the substrate surface around the edges of the IC chip and capillary action is then relied upon to draw the epoxy into the low-profile gap. Undesirable air pockets which otherwise would develop form the displaced air as the epoxy flows into the low-profile gap can advantageously escape through the aperture of the invention.
摘要:
The specification describes techniques for attaching double sided circuit boards having plated through holes to interconnection substrates using solder bump arrays. The through holes are filled with a high melting point solder which allows solder bumps to be located directly on the through hole thus saving board area and reducing the interconnection length.
摘要:
A novel packaging of semiconductor elements, such as MCM tiles, with a variety of printed circuit or wired boards (PWB), the packages occupying a small size, at least in the vertical direction, relative to prior art OMPAC devices. The MCM tile includes an interconnection substrate with peripheral metallizations and at least one chip or integrated circuit (IC) mounted on the substrate by solder reflow or conductive adhesive technology. The PWB which may be a single level or a multilevel, is provided with an aperture for accommodation of at least one chip therein. Depending on the type of interconnection between the substrate and the PWB, the aperture may be larger than the substrate of the MCM tile for wire bonding interconnection or smaller than the substrate for solder reflow or conductive adhesive interconnection. In the wire bonding case, the MCM tile is positioned within the aperture resting on the surface of the PWB or of a structural member or of a heat sink which encloses one end of the aperture. The other end of the aperture may be open or enclosed by a structural member, a heat sink, another PWB or a mother board. For solder reflow or conductive adhesive interconnection, the substrate which is larger than the aperture is positioned so that its ends overlap areas of the PWB adjacent the aperture and the chips and/or substrate are positioned within the aperture. The interconnections are enclosed in a compliable encapsulating material, such as silica gel.