公开(公告)号：US20130009286A1

公开(公告)日：2013-01-10

申请号：US13471735

申请日：2012-05-15

申请人： Young-lyong Kim ,  Jong-ho Lee ,  Moon-gi Cho ,  Hwan-sik Lim ,  Sun-hee Park

发明人： Young-lyong Kim ,  Jong-ho Lee ,  Moon-gi Cho ,  Hwan-sik Lim ,  Sun-hee Park

IPC分类号： H01L23/58

CPC分类号： H01L24/11 ,  H01L23/3128 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/32 ,  H01L24/81 ,  H01L2224/02123 ,  H01L2224/0331 ,  H01L2224/0332 ,  H01L2224/0345 ,  H01L2224/03464 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05016 ,  H01L2224/05017 ,  H01L2224/05018 ,  H01L2224/05019 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05025 ,  H01L2224/05026 ,  H01L2224/05027 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05166 ,  H01L2224/0519 ,  H01L2224/05191 ,  H01L2224/05556 ,  H01L2224/05558 ,  H01L2224/05559 ,  H01L2224/0556 ,  H01L2224/05562 ,  H01L2224/05568 ,  H01L2224/05666 ,  H01L2224/0569 ,  H01L2224/05691 ,  H01L2224/1131 ,  H01L2224/1132 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/11912 ,  H01L2224/13013 ,  H01L2224/13014 ,  H01L2224/13017 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13084 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13166 ,  H01L2224/1319 ,  H01L2224/13191 ,  H01L2224/14131 ,  H01L2224/1416 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/1435 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/01074 ,  H01L2924/014 ,  H01L2224/05552 ,  H01L2924/00

摘要： A semiconductor chip includes stress-relief to mitigate the effects of differences in coefficients of thermal expansion (CTE) between a printed circuit board (PCB) and a semiconductor chip and a flip-chip package including the semiconductor chip. The semiconductor chip includes a stress-relief buffer coupling a bump and a semiconductor chip pad.

摘要翻译： 半导体芯片包括减轻压力以减轻印刷电路板（PCB）和半导体芯片之间的热膨胀系数（CTE）的差异以及包括半导体芯片的倒装芯片封装的影响。 半导体芯片包括耦合凸块的应力消除缓冲器和半导体芯片焊盘。

公开(公告)号：US09245816B2

公开(公告)日：2016-01-26

申请号：US14328668

申请日：2014-07-10

申请人： Chul-yong Jang ,  Young-lyong Kim ,  Ae-nee Jang

发明人： Chul-yong Jang ,  Young-lyong Kim ,  Ae-nee Jang

IPC分类号： H01L23/48 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L21/56 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00

CPC分类号： H01L25/0657 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/27 ,  H01L24/32 ,  H01L24/73 ,  H01L24/82 ,  H01L24/96 ,  H01L25/50 ,  H01L2224/11849 ,  H01L2224/12105 ,  H01L2224/13023 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/14155 ,  H01L2224/16058 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/2746 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/48228 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81447 ,  H01L2224/81815 ,  H01L2224/8203 ,  H01L2224/92244 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06562 ,  H01L2225/06586 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2224/83 ,  H01L2224/11 ,  H01L2924/00 ,  H01L2924/00012

摘要： Embodiments of the inventive concept include a semiconductor package having a plurality of stacked semiconductor chips. A multi-layered substrate includes a central insulation layer, an upper wiring layer disposed on an upper surface of the central insulation layer, and a first lower wiring layer disposed on a lower surface of the central insulation layer. The stacked semiconductor chips are connected to the multi-layered substrate and/or each other using various means. The semiconductor package is capable of high performance operation, like a semiconductor package based on flip-ship bonding, and also meets the need for large capacity by overcoming a limitation caused by a single semiconductor chip. Embodiments of the inventive concept also include methods of manufacturing the semiconductor package.

摘要翻译： 本发明构思的实施例包括具有多个堆叠的半导体芯片的半导体封装。 多层基板包括中心绝缘层，设置在中心绝缘层的上表面上的上布线层和设置在中心绝缘层的下表面上的第一下布线层。 堆叠的半导体芯片使用各种手段连接到多层基板和/或彼此。 该半导体封装能够进行高性能的操作，例如基于翻转式接合的半导体封装，并且通过克服由单个半导体芯片引起的限制来满足大容量的需要。 本发明构思的实施例还包括制造半导体封装的方法。

公开(公告)号：US20080017968A1

公开(公告)日：2008-01-24

申请号：US11812580

申请日：2007-06-20

申请人： Young-shin Choi ,  Young-lyong Kim ,  Kun-dae Yeom

发明人： Young-shin Choi ,  Young-lyong Kim ,  Kun-dae Yeom

IPC分类号： H01L23/02 ,  H01L21/00

CPC分类号： H01L23/3128 ,  H01L21/565 ,  H01L21/568 ,  H01L23/49811 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/07802 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/0401 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A stack type semiconductor package, and a method of fabricating the same are provided. The stack type semiconductor package may include a lower unit package and an upper unit package. The lower unit package may include a substrate, and a semiconductor chip on an upper surface of the substrate. A bump may be on an upper surface of the substrate, and a protecting layer, covering the semiconductor chip, may be formed. The protecting layer may include a via hole partially exposing the bump. The upper unit package may be on the protecting layer, and may include an internal connection solder ball on a lower surface of the upper unit package. The internal connection solder ball may be inserted into the via hole and connected to the bump.

摘要翻译： 提供了堆叠型半导体封装及其制造方法。 叠层型半导体封装可以包括下单元封装和上单元封装。 下单元封装可以包括衬底，以及在衬底的上表面上的半导体芯片。 凸块可以在基板的上表面上，并且可以形成覆盖半导体芯片的保护层。 保护层可以包括部分地暴露凸块的通孔。 上部单元封装可以在保护层上，并且可以包括在上部单元封装的下表面上的内部连接焊球。 内部连接焊球可以插入通孔并连接到凸块。