公开(公告)号：US06805219B2

公开(公告)日：2004-10-19

申请号：US10205207

申请日：2002-07-26

申请人： Zenichi Yasuda ,  Yutaka Ogasawara ,  Yoshikazu Hirose ,  Yasuo Sakakibara ,  Masahiro Ogata

发明人： Zenichi Yasuda ,  Yutaka Ogasawara ,  Yoshikazu Hirose ,  Yasuo Sakakibara ,  Masahiro Ogata

IPC分类号： F01N1100

CPC分类号： F02B77/13 ,  F02F7/006

摘要： An engine cover has a cover body having a through hole penetrating both sides of the cover body in an area opposed to a resonant space in which resonant sounds are generated. An opening of the through hole is covered with the sound absorbing member layer. Because a part of the resonant space is open, resonant sounds generated in the resonance space are decreased.

摘要翻译： 发动机盖具有盖主体，该盖主体在与产生共鸣声的共振空间相对的区域中贯穿盖体的两侧。 通孔的开口被吸音构件层覆盖。 由于共振空间的一部分是开放的，共振空间中产生的共振声音减小。

公开(公告)号：US06800685B1

公开(公告)日：2004-10-05

申请号：US09590814

申请日：2000-06-09

申请人： Nori Yoshihara ,  Satoshi Kosugi ,  Kenjiro Ogami ,  Hidehiro Nakamura ,  Yutaka Ogasawara ,  Masahiro Ogata ,  Satoru Watanabe ,  Junji Koizumi

发明人： Nori Yoshihara ,  Satoshi Kosugi ,  Kenjiro Ogami ,  Hidehiro Nakamura ,  Yutaka Ogasawara ,  Masahiro Ogata ,  Satoru Watanabe ,  Junji Koizumi

IPC分类号： C08K334

CPC分类号： C08L67/02 ,  C08K3/013 ,  C08K3/08 ,  C08K3/34 ,  C08K7/14 ,  C08L23/0815 ,  C08L23/0869 ,  C08L23/0884 ,  C08L23/147 ,  C08L2205/02 ,  C08L2666/02 ,  C08L2666/06

摘要： The present invention provides a polyester resin composition for engine peripheral parts, the resin composition comprising at least one polymer selected from the group consisting of polyethylene terephthalate and an ethylene terephthalate copolymer; an inorganic reinforcement material; and an olefin polymer, wherein a molded article produced from the resin composition has a flexural strain at break of 3.5% or higher and a deflection temperature under load of 180° C. or higher.

摘要翻译： 本发明提供一种用于发动机周边部件的聚酯树脂组合物，该树脂组合物包含至少一种选自聚对苯二甲酸乙二醇酯和对苯二甲酸乙二醇酯共聚物的聚合物; 无机增强材料; 和烯烃聚合物，其中由树脂组合物制备的模制品的弯曲应变为3.5％以上，负荷挠曲温度为180℃以上。

公开(公告)号：US5313423A

公开(公告)日：1994-05-17

申请号：US754019

申请日：1991-09-03

申请人： Katsuyuki Sato ,  Miki Matsumoto ,  Sadayuki Ohkuma ,  Masahiro Ogata ,  Masahiro Yoshida

发明人： Katsuyuki Sato ,  Miki Matsumoto ,  Sadayuki Ohkuma ,  Masahiro Ogata ,  Masahiro Yoshida

IPC分类号： G11C29/00 ,  G11C7/10 ,  G11C7/18 ,  G11C8/10 ,  G11C11/401 ,  G11C29/04 ,  G11C13/00

CPC分类号： G11C7/18 ,  G11C7/1075 ,  G11C8/10

摘要： A multiport memory is provided which permits both random access and serial access. In order to reduce parasitic capacitance and improve operating speed, the serial input/output lines are each divided into two parts at their middle points. Sense amplifiers for the serial input/output lines are provided at upper and lower ends of the serial access memory elements to respectively amplify signals from the divided lines. Additional features are provided for improving both the serial and random operation. For example, during the serial read mode, the column selector for random access is simultaneously operated, and read data passing through the random access column selector is used as head data for the serial output operation to be delivered through the serial output circuit. Also, a serial selector can be controlled by a select signal formed by a Gray Code counter to improve operating speed. Further features included a redundancy system for relief of defective bits, the use of common bit lines to improve integration density and an improved refreshing arrangement to reduce power consumption during the refresh mode.

公开(公告)号：US5161120A

公开(公告)日：1992-11-03

申请号：US496531

申请日：1990-03-20

申请人： Takeshi Kajimoto ,  Yutaka Shimbo ,  Katsuyuki Sato ,  Masahiro Ogata ,  Kanehide Kenmizaki ,  Shouji Kubono ,  Nobuo Kato ,  Kiichi Manita ,  Michitaro Kanamitsu

发明人： Takeshi Kajimoto ,  Yutaka Shimbo ,  Katsuyuki Sato ,  Masahiro Ogata ,  Kanehide Kenmizaki ,  Shouji Kubono ,  Nobuo Kato ,  Kiichi Manita ,  Michitaro Kanamitsu

IPC分类号： G01R31/26 ,  G01R31/28 ,  G11C11/401 ,  G11C11/403 ,  G11C11/406 ,  G11C11/407 ,  G11C11/408 ,  G11C11/409 ,  G11C11/4093 ,  G11C29/00 ,  G11C29/02 ,  G11C29/14 ,  G11C29/50 ,  H01L21/82 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/10 ,  H01L27/108 ,  H03K3/037 ,  H03K19/096

CPC分类号： G11C29/027 ,  G11C11/406 ,  G11C11/4093 ,  G11C29/02 ,  G11C29/50 ,  G11C29/50012 ,  G11C29/50016 ,  G11C2029/5004

摘要： A data output buffer is provided in connection with a semiconductor memory, such as a pseudostatic RAM, which is capable of high speed operation with respect to memory data readout. The buffer includes a latch circuit comprising a pair of NAND gate circuits having input and output terminals connected in cross connection, a pair of precharge MOSFETs provided respectively between the noninverted and inverted input terminals of the latch circuit, a pair of CMOS NAND gates which transfer the inverted signal of the latch circuit according to an inverted timing signal and a pair of series-connected MOSFETs effecting a pull-up/pull-down arrangement which receives the inverted signal of the output signal of the NAND gates.

摘要翻译： 数据输出缓冲器与诸如伪稳态RAM的半导体存储器相关地提供，其能够相对于存储器数据读出而进行高速操作。 该缓冲器包括一个锁存电路，该锁存电路包括一对具有交叉连接的输入和输出端的NAND门电路，分别设置在锁存电路的非反相和反相输入端之间的一对预充电MOSFET，一对转换 根据反相定时信号的锁存电路的反相信号和实现上拉/下拉布置的一对串联MOSFET，其接收NAND门输出信号的反相信号。

公开(公告)号：US4437135A

公开(公告)日：1984-03-13

申请号：US319077

申请日：1981-11-06

申请人： Masahiro Ogata ,  Osamu Sakai

发明人： Masahiro Ogata ,  Osamu Sakai

IPC分类号： H03F1/52 ,  G11C11/408 ,  G11C11/418 ,  H01L21/8234 ,  H01L27/02 ,  H01L27/06 ,  H01L27/088 ,  H01L29/78 ,  H02H7/20 ,  H03F1/42 ,  H02H9/04

CPC分类号： H01L27/0251 ,  G11C11/4082 ,  G11C11/418 ,  H01L29/78 ,  H01L2924/0002

摘要： In the past, it has been a problem in integrated circuits using MOSFETs that the gate insulating film of a transmission gate MOSFET is broken down when an abnormally high voltage such as is caused by frictional static electricity is applied to its drain region. This breakdown of the gate insulating film cannot be prevented merely by limiting the voltage level applied to the drain region to a level below the breakdown withstand voltage of the gate insulating film. The reason for this is that even with such voltage limiting, the breakdown of the gate insulating film can still occur when local heating is generated by a relatively large breakdown current flowing through the drain junction. To prevent such a breakdown of the gate insulating film, therefore, a resistance element for limiting the breakdown current is connected in series with the drain region of the transmission gate MOSFET.

摘要翻译： 过去，在使用MOSFET的集成电路中，当由于摩擦静电引起的异常高电压被施加到其漏极区域时，传输栅极MOSFET的栅极绝缘膜被分解的问题。 栅极绝缘膜的击穿不能仅通过将施加到漏极区域的电压电平限制在低于栅极绝缘膜的击穿耐受电压的水平来防止。 其原因在于，即使采用这种电压限制，当通过流过漏极连接点的较大的击穿电流产生局部加热时，栅极绝缘膜的击穿仍然可能发生。 因此，为了防止栅极绝缘膜的这种击穿，用于限制击穿电流的电阻元件与传输栅极MOSFET的漏极区域串联连接。

公开(公告)号：US08643047B2

公开(公告)日：2014-02-04

申请号：US13414458

申请日：2012-03-07

申请人： Kozo Uemura ,  Soichi Shibusawa ,  Yumiko Hayashida ,  Kiyoshi Nishimura ,  Seiko Kawashima ,  Tsuyoshi Oyaizu ,  Masahiro Ogata ,  Shuhei Matsuda ,  Hiroki Tamai

发明人： Kozo Uemura ,  Soichi Shibusawa ,  Yumiko Hayashida ,  Kiyoshi Nishimura ,  Seiko Kawashima ,  Tsuyoshi Oyaizu ,  Masahiro Ogata ,  Shuhei Matsuda ,  Hiroki Tamai

IPC分类号： H01L33/00

CPC分类号： H05K3/284 ,  F21S8/04 ,  F21V19/0055 ,  F21Y2115/10 ,  H01L25/0753 ,  H01L33/56 ,  H01L33/60 ,  H01L2224/48091 ,  H01L2224/73265 ,  H05K1/0209 ,  H05K3/244 ,  H05K2201/0162 ,  H05K2201/099 ,  H05K2201/10106 ,  H05K2201/2054 ,  H01L2924/00014 ,  H01L2924/00

摘要： A light-emitting device includes a substrate, a reflecting layer formed on the substrate, a light-emitting element placed on the reflecting layer, and a sealing resin layer that covers the reflecting layer and the light-emitting element. The oxygen permeability of the sealing resin layer is equal to or lower than 1200 cm3/(m2·day·atm), and the ratio of the area of the reflecting layer covered by the sealing resin layer to the entire area on the resin substrate covered by the sealing resin layer is between 30% and 75% inclusive.

摘要翻译： 发光装置包括基板，形成在基板上的反射层，放置在反射层上的发光元件和覆盖反射层和发光元件的密封树脂层。 密封树脂层的透氧度等于或低于1200cm3 /（m2·day·atm），并且覆盖在树脂基板上的密封树脂层覆盖的反射层的面积与覆盖的整个面积的比率 通过密封树脂层在30％和75％之间。

公开(公告)号：US20130025254A1

公开(公告)日：2013-01-31

申请号：US13641076

申请日：2011-04-11

申请人： So Kurosaka ,  Mitsugu Ashikaga ,  Masahiro Ogata ,  Yasufumi Hosokawa ,  Muneyuki Nishi ,  Tsuyoshi Sato

发明人： So Kurosaka ,  Mitsugu Ashikaga ,  Masahiro Ogata ,  Yasufumi Hosokawa ,  Muneyuki Nishi ,  Tsuyoshi Sato

IPC分类号： F02C9/00

CPC分类号： F23N1/042 ,  F02C3/205 ,  F02C9/28 ,  F23C13/02 ,  F23N5/022 ,  F23N2023/54 ,  F23N2037/12 ,  F23N2037/20 ,  F23N2041/20 ,  F23R3/40

摘要： Provided is a controller for use with a gas turbine engine, which ensures a stable combustion regardless of the deterioration of the catalyst and elevated characteristics of the exhaust gas. The controller 6 is used in the engine which comprises a combustor 2 for combusting a mixture of compressed air from a compressor 1 and a fuel under the existence of catalyst, the combustor having a catalytic combustion unit 21 bearing the catalyst and a pre-burner 7 provided on an upstream side of the catalytic combustion unit with respect to a flow of the compressed air for supplying and combusting a pre-heating fuel PF with the compressed air CA. The controller comprises a memory 6c for memorizing an initial temperature difference D between inlet and outlet temperatures t1, t2 measured at inlet and outlet of the catalytic combustion unit with non-deteriorated catalyst accommodated therein, and a pre-burner control for calculating a present temperature difference between the inlet and outlet temperatures measured in an operation of the gas turbine engine and controlling an amount of the fuel to be supplied to the pre-burner according to a deterioration Δd of the catalyst which is provided by a difference between the initial and present temperature differences D and d.

摘要翻译： 提供了一种与燃气涡轮发动机一起使用的控制器，其确保了稳定的燃烧，而不管催化剂的劣化和排气的特性如何。 控制器6用于发动机中，该发动机包括用于在存在催化剂的情况下燃烧来自压缩机1的压缩空气和燃料的混合物的燃烧器2，该燃烧器具有带催化剂的催化燃烧单元21和预燃烧器7 设置在催化燃烧单元的上游侧，相对于用于将预热燃料PF与压缩空气CA供应和燃烧的压缩空气流。 该控制器包括一个存储器6c，用于存储在其中容纳有未劣化的催化剂的催化燃烧单元的入口和出口处测得的入口和出口温度t1，t2之间的初始温度差D，以及用于计算当前温度的预燃烧器控制 根据燃料涡轮发动机的运行中测量的入口和出口温度之间的差异，并且根据催化剂的劣化和Dgr d来控制供应到预燃烧器的燃料量，其由初始 并存在温差D和d。

公开(公告)号：US07082919B2

公开(公告)日：2006-08-01

申请号：US10808525

申请日：2004-03-25

申请人： Haruhiko Nonogaki ,  Itsuro Maeda ,  Masahiro Ogata

发明人： Haruhiko Nonogaki ,  Itsuro Maeda ,  Masahiro Ogata

IPC分类号： F02B77/11

CPC分类号： F16B21/073 ,  F02F7/006 ,  F16B21/075

摘要： A mounting structure for an engine cover includes: a protruded member which has a neck and a head with a larger diameter than the neck; and a recessed member which has an external circumferential surface small diameter section to be locked to a mounting hole of a mounting seat arranged so as to be opposed to the protruded member, and a concave holding the head of the press-fit protruded member. In the protruded member, at least a portion surrounding the concave is formed solid. The head is arranged closer to a rear surface of the engine cover than the mounting hole. A compression space, which is compressed in the case in which a collision load equal to or larger than a predetermined value is applied in a front and rear direction of the engine cover, is defined between the recessed member and the rear surface of the engine cover.

摘要翻译： 用于发动机盖的安装结构包括：突出部件，其具有颈部和具有比颈部更大的直径的头部; 以及具有外周面小直径部分的凹入部件，该外部圆周表面小直径部分被锁定到与突出部件相对设置的安装座的安装孔，以及保持压配突起部件的头部的凹部。 在突出部件中，围绕凹部的至少一部分形成为固体。 头部布置成比安装孔更靠近发动机罩的后表面。 在发动机盖的前后方向上施加碰撞载荷等于或大于预定值的情况下被压缩的压缩空间被限定在发动机盖的凹部和后表面之间 。

公开(公告)号：US5419994A

公开(公告)日：1995-05-30

申请号：US939989

申请日：1992-09-03

申请人： Toshio Honjo ,  Yuji Sato ,  Kanao Kayamoto ,  Masahiro Ogata

发明人： Toshio Honjo ,  Yuji Sato ,  Kanao Kayamoto ,  Masahiro Ogata

IPC分类号： G03G9/10 ,  G03G9/107

CPC分类号： G03G9/10

摘要： An iron carrier for an electrophotographic developer, the carrier having a mean particle diameter of 25 to 40 .mu.m, a magnetization of at least 160 emu/g at 3000 Oe, an apparent density of 3.0 to 4.2 g/cm.sup.3, a percentage sphericity of at least 80%, and a specific surface area of at least 350 cm.sup.2 /g as determined by an air permeation method; a process for preparing the carrier by a plasma method; and an electrophotographic developer comprising the carrier.

摘要翻译： 用于电子照相显影剂的铁载体，该载体的平均粒径为25〜40μm，在3000Oe下的磁化强度至少为160emu / g，表观密度为3.0〜4.2g / cm 3，球形度的百分比 至少80％，和通过空气渗透法测定的至少350cm 2 / g的比表面积; 通过等离子体法制备载体的方法; 和包含载体的电子照相显影剂。

公开(公告)号：US5311476A

公开(公告)日：1994-05-10

申请号：US943341

申请日：1992-06-18

申请人： Takeshi Kajimoto ,  Yutaka Shimbo ,  Katsuyuki Sato ,  Masahiro Ogata ,  Kanehide Kenmizaki ,  Shouji Kubono ,  Nobuo Kato ,  Kiichi Manita ,  Michitaro Kanamitsu

发明人： Takeshi Kajimoto ,  Yutaka Shimbo ,  Katsuyuki Sato ,  Masahiro Ogata ,  Kanehide Kenmizaki ,  Shouji Kubono ,  Nobuo Kato ,  Kiichi Manita ,  Michitaro Kanamitsu

IPC分类号： G01R31/26 ,  G01R31/28 ,  G11C11/401 ,  G11C11/403 ,  G11C11/406 ,  G11C11/407 ,  G11C11/408 ,  G11C11/409 ,  G11C11/4093 ,  G11C29/00 ,  G11C29/02 ,  G11C29/14 ,  G11C29/50 ,  H01L21/82 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/10 ,  H01L27/108 ,  H03K3/037 ,  H03K19/096

CPC分类号： G11C29/027 ,  G11C11/406 ,  G11C11/4093 ,  G11C29/02 ,  G11C29/50 ,  G11C29/50012 ,  G11C29/50016 ,  G11C2029/5004

摘要： There is provided in connection with a semiconductor memory, such as of the pseudostatic RAM, a layout of the circuit components thereof including a method of testing the memory. There is provided an oscillation circuit which is capable of withstanding bumping of the power source voltage (varying) which effects stabilization regarding the operation of the circuits included therewith including a refresh timer circuit. There is also provided for testing a refresh timer circuit and a semiconductor memory which includes a refresh timer circuit. There is further provided for an output buffer which is capable of high speed operation with respect to memory data readout, a voltage generating circuit which is capable of stable operation and a fuse circuit, such as provided in connection with redundant circuitry in the memory and which is characterized as having a configuration of a fuse logic gate circuit employing complementary channel MOSFETs together with a fuse. With respect to the semiconductor memory, such as the pseudostatic RAM, the initial count of the refresh timer counter circuit of the refresh timer circuit can be set at an optional value by applying a signal to an address input terminal, and a test mode can be effected in which the refresh period can be set at an optional value by accordingly applying a test control signal to a predetermined external terminal. Therefore, the discharge current of the oscillation circuit capacitor associated with the refresh timer circuit becomes stabilized, noting the particular layout arrangement regarding the polycrystalline silicon layer forming the resistor of the oscillation circuit, and the fact that same parasitic capacitances are effectively connected between the polycrystalline silicon resistor and the supply voltage of the circuit and between the polycrystalline silicon resistor and the ground potential of the circuit thereby cancelling any variation of the output of the power source. Therefore, variation of the oscillation frequency of the oscillation circuit attributable to the bumping of the power source can be effectively suppressed.