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1.发明授权Semiconductor device and method of forming wafer-level multi-row etched leadframe with base leads and embedded semiconductor die 有权用基极引线和嵌入式半导体芯片形成晶圆级多行蚀刻引线框的半导体器件和方法公开(公告)号：US08993376B2
公开(公告)日：2015-03-31
申请号：US13284811
申请日：2011-10-28
IPC分类号： H01L21/00 , H01L23/00 , H01L25/065 , H01L25/10 , H01L25/00 , H01L23/495 , H01L21/48 , H01L25/16
CPC分类号： H01L24/29 , H01L21/4832 , H01L23/49548 , H01L23/49575 , H01L23/49582 , H01L24/16 , H01L24/19 , H01L24/32 , H01L24/48 , H01L24/73 , H01L24/81 , H01L24/85 , H01L24/92 , H01L25/0657 , H01L25/105 , H01L25/16 , H01L25/50 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/16225 , H01L2224/16227 , H01L2224/16245 , H01L2224/29111 , H01L2224/2919 , H01L2224/32014 , H01L2224/32145 , H01L2224/48247 , H01L2224/73253 , H01L2224/73265 , H01L2224/73267 , H01L2224/81191 , H01L2224/81411 , H01L2224/81424 , H01L2224/81439 , H01L2224/81444 , H01L2224/81447 , H01L2224/81455 , H01L2224/83805 , H01L2224/85411 , H01L2224/85424 , H01L2224/85439 , H01L2224/85444 , H01L2224/85447 , H01L2224/85455 , H01L2224/92247 , H01L2225/0651 , H01L2225/06517 , H01L2225/06558 , H01L2225/1023 , H01L2225/1029 , H01L2225/1035 , H01L2225/1052 , H01L2225/1058 , H01L2225/107 , H01L2924/00011 , H01L2924/00014 , H01L2924/01014 , H01L2924/01029 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/0132 , H01L2924/01322 , H01L2924/014 , H01L2924/12041 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/1432 , H01L2924/1433 , H01L2924/14335 , H01L2924/1434 , H01L2924/15311 , H01L2924/1579 , H01L2924/181 , H01L2924/00 , H01L2224/45099 , H01L2924/0105 , H01L2924/01082 , H01L2924/00012 , H01L2224/13111 , H01L2924/0665 , H01L2224/81805
摘要： A semiconductor device has a base substrate with first and second opposing surfaces. A plurality of cavities and base leads between the cavities is formed in the first surface of the base substrate. The first set of base leads can have a different height or similar height as the second set of base leads. A concave capture pad can be formed over the second set of base leads. Alternatively, a plurality of openings can be formed in the base substrate and the semiconductor die mounted to the openings. A semiconductor die is mounted between a first set of the base leads and over a second set of the base leads. An encapsulant is deposited over the die and base substrate. A portion of the second surface of the base substrate is removed to separate the base leads. An interconnect structure is formed over the encapsulant and base leads.
摘要翻译： 半导体器件具有带有第一和第二相对表面的基底基板。 在基底基板的第一表面中形成有在空腔之间的多个空腔和基底引线。 第一组基线可以具有与第二组基线不同的高度或相似的高度。 可以在第二组基线上形成凹形捕获垫。 或者，可以在基底基板和安装到开口的半导体管芯上形成多个开口。 半导体管芯安装在第一组基极引线之间和第二组基极引线之间。 密封剂沉积在管芯和基底衬底上。 去除基底基板的第二表面的一部分以分离基底引线。 在密封剂和基底引线上形成互连结构。
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2.发明申请Semiconductor Device and Method of Forming EWLB Package With Standoff Conductive Layer Over Encapsulant Bumps 有权半导体器件和形成EWLB封装的隔离导电层在封装冲击波上的方法公开(公告)号：US20120326337A1
公开(公告)日：2012-12-27
申请号：US13167133
申请日：2011-06-23
CPC分类号： H01L24/96 , H01L21/561 , H01L21/568 , H01L24/19 , H01L24/20 , H01L24/97 , H01L25/105 , H01L2224/04105 , H01L2224/19 , H01L2224/96 , H01L2224/97 , H01L2225/1035 , H01L2924/00 , H01L2924/01029 , H01L2924/01322 , H01L2924/014 , H01L2924/07802 , H01L2924/12041 , H01L2924/12042 , H01L2924/1306 , H01L2924/13091 , H01L2924/15747 , H01L2924/181 , H01L2924/1815 , H01L2924/00012
摘要： A semiconductor device has a carrier with a die attach area. Recesses are formed partially through the carrier outside the die attach area. A first conductive layer is conformally applied over a surface of the carrier and into the recesses. A semiconductor die is mounted to the die attach area of the carrier. An encapsulant is deposited over the carrier and semiconductor die. The encapsulant extends into the recesses over the first conductive layer to form encapsulant bumps. The carrier is removed to expose the first conductive layer over the encapsulant bumps. A first insulating layer is formed over the semiconductor die with openings to expose contact pads of the semiconductor die. A second conductive layer is formed between the first conductive layer and the contact pads on the semiconductor die. A second insulating layer is formed over the second conductive layer and semiconductor die.
摘要翻译： 半导体器件具有带有裸片附着区域的载体。 凹槽部分地通过载体在芯片附着区域外部形成。 第一导电层保形地施加在载体的表面上并进入凹部。 将半导体管芯安装到载体的管芯附着区域。 封装剂沉积在载体和半导体管芯上。 密封剂延伸到第一导电层上的凹槽中以形成密封剂凸块。 去除载体以将第一导电层暴露在密封剂凸块之上。 在半导体管芯上形成第一绝缘层，具有开口以露出半导体管芯的接触焊盘。 在第一导电层和半导体管芯上的接触焊盘之间形成第二导电层。 在第二导电层和半导体管芯上形成第二绝缘层。
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3.发明申请Semiconductor Device and Method of Forming Wafer Level Multi-Row Etched Lead Package 审中-公开半导体器件和形成晶圆级多行蚀刻引线封装的方法公开(公告)号：US20120273927A1
公开(公告)日：2012-11-01
申请号：US13543637
申请日：2012-07-06
IPC分类号： H01L23/552
CPC分类号： H01L21/56 , H01L23/28 , H01L25/11 , H01L2224/04105 , H01L2224/12105 , H01L2224/24247 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/48091 , H01L2224/48229 , H01L2224/48235 , H01L2224/73265 , H01L2224/73267 , H01L2224/92244 , H01L2924/01322 , H01L2924/13091 , H01L2924/15153 , H01L2924/15311 , H01L2924/181 , H01L2924/18162 , H01L2924/3025 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： A semiconductor device has a base carrier having first and second opposing surfaces. The first surface of the base carrier is etched to form a plurality of cavities and multiple rows of base leads between the cavities extending between the first and second surfaces. A second conductive layer is formed over the second surface of the base carrier. A semiconductor die is mounted within a cavity of the base carrier. A first insulating layer is formed over the die and first surface of the base carrier and into the cavities. A first conductive layer is formed over the first insulating layer and first surface of the base carrier. A second insulating layer is formed over the first insulating layer and first conductive layer. A portion of the second surface of the base carrier is removed to expose the first insulating layer and electrically isolate the base leads.
摘要翻译： 半导体器件具有具有第一和第二相对表面的基底载体。 基底托架的第一表面被蚀刻以形成在第一和第二表面之间延伸的空腔之间的多个空腔和多排基底引线。 第二导电层形成在基底载体的第二表面上。 半导体管芯安装在基座的空腔内。 第一绝缘层形成在基体载体的模具和第一表面上并进入空腔中。 在第一绝缘层和基底载体的第一表面上形成第一导电层。 在第一绝缘层和第一导电层上形成第二绝缘层。 去除基底载体的第二表面的一部分以露出第一绝缘层并电绝缘基极。
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4.发明申请Semiconductor Device and Method of Forming Leadframe Interposer Over Semiconductor Die and TSV Substrate for Vertical Electrical Interconnect 有权半导体器件和形成用于垂直电互连的半导体芯片和TSV基板的引线框架插入件的方法公开(公告)号：US20120061814A1
公开(公告)日：2012-03-15
申请号：US12882110
申请日：2010-09-14
IPC分类号： H01L23/495 , H01L21/60
CPC分类号： H01L23/495 , H01L21/4832 , H01L21/4853 , H01L21/56 , H01L21/563 , H01L23/3107 , H01L23/3128 , H01L23/3135 , H01L23/49811 , H01L23/49816 , H01L23/49827 , H01L24/03 , H01L24/05 , H01L24/16 , H01L24/29 , H01L24/32 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/81 , H01L25/03 , H01L25/0657 , H01L25/105 , H01L2224/0345 , H01L2224/03452 , H01L2224/03462 , H01L2224/03464 , H01L2224/0401 , H01L2224/04042 , H01L2224/05611 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/06131 , H01L2224/16225 , H01L2224/29144 , H01L2224/2919 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48105 , H01L2224/48157 , H01L2224/48175 , H01L2224/48227 , H01L2224/48228 , H01L2224/48247 , H01L2224/49113 , H01L2224/73204 , H01L2224/73253 , H01L2224/73265 , H01L2224/81411 , H01L2224/81424 , H01L2224/81439 , H01L2224/81444 , H01L2224/81447 , H01L2224/81455 , H01L2224/831 , H01L2225/06517 , H01L2225/1023 , H01L2225/1041 , H01L2225/1058 , H01L2924/00011 , H01L2924/00014 , H01L2924/01079 , H01L2924/01322 , H01L2924/12041 , H01L2924/12042 , H01L2924/13091 , H01L2924/14 , H01L2924/15311 , H01L2924/157 , H01L2924/1579 , H01L2924/181 , H01L2924/1815 , H01L2924/3511 , H05K2203/0384 , H01L2924/01014 , H01L2924/0665 , H01L2924/00 , H01L2924/00012 , H01L2224/81805 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor device has a substrate with a plurality of conductive vias formed through the substrate and first conductive layer formed over the substrate. A first semiconductor die is mounted over the substrate. A second semiconductor die can be mounted over the first semiconductor die. A leadframe interposer has a base plate and a plurality of base leads extending from the base plate. An etch-resistant conductive layer is formed over a surface of the base plate opposite the base leads. The leadframe is mounted to the substrate over the first semiconductor die. An encapsulant is deposited over the substrate and first semiconductor die. The base plate is removed while retaining the etch-resistant conductive layer and portion of the base plate opposite the base leads to electrically isolate the base leads. An interconnect structure is formed over a surface of the substrate opposite the base leads.
摘要翻译： 半导体器件具有衬底，其具有通过衬底形成的多个导电通孔和形成在衬底上的第一导电层。 第一半导体管芯安装在衬底上。 第二半导体管芯可以安装在第一半导体管芯上。 引线框架插入件具有基板和从基板延伸的多个基底引线。 在与基极相对的基板的表面上形成耐蚀刻导电层。 引线框架安装在第一半导体管芯上的衬底上。 密封剂沉积在衬底和第一半导体管芯上。 去除基板，同时保持耐蚀刻导电层，并且基板的与基底引线相对的部分电绝缘基极。 在与基极相对的基板的表面上形成互连结构。
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5.发明申请Semiconductor Device and Method of Forming Wafer Level Multi-Row Etched Lead Package 有权半导体器件和形成晶圆级多行蚀刻引线封装的方法公开(公告)号：US20110215449A1
公开(公告)日：2011-09-08
申请号：US12719476
申请日：2010-03-08
CPC分类号： H01L21/56 , H01L23/28 , H01L25/11 , H01L2224/04105 , H01L2224/12105 , H01L2224/24247 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/48091 , H01L2224/48229 , H01L2224/48235 , H01L2224/73265 , H01L2224/73267 , H01L2224/92244 , H01L2924/01322 , H01L2924/13091 , H01L2924/15153 , H01L2924/15311 , H01L2924/181 , H01L2924/18162 , H01L2924/3025 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： A semiconductor device has a base carrier having first and second opposing surfaces. The first surface of the base carrier is etched to form a plurality of cavities and multiple rows of base leads between the cavities extending between the first and second surfaces. A second conductive layer is formed over the second surface of the base carrier. A semiconductor die is mounted within a cavity of the base carrier. A first insulating layer is formed over the die and first surface of the base carrier and into the cavities. A first conductive layer is formed over the first insulating layer and first surface of the base carrier. A second insulating layer is formed over the first insulating layer and first conductive layer. A portion of the second surface of the base carrier is removed to expose the first insulating layer and electrically isolate the base leads.
摘要翻译： 半导体器件具有具有第一和第二相对表面的基底载体。 基底托架的第一表面被蚀刻以形成在第一和第二表面之间延伸的空腔之间的多个空腔和多排基底引线。 第二导电层形成在基底载体的第二表面上。 半导体管芯安装在基座的空腔内。 第一绝缘层形成在基体载体的模具和第一表面上并进入空腔中。 在第一绝缘层和基底载体的第一表面上形成第一导电层。 在第一绝缘层和第一导电层上形成第二绝缘层。 去除基底载体的第二表面的一部分以露出第一绝缘层并电绝缘基极。
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6.发明授权Semiconductor device and method of forming EWLB package with standoff conductive layer over encapsulant bumps 有权半导体器件和在密封剂凸块上形成具有隔离导电层的EWLB封装的方法公开(公告)号：US09006031B2
公开(公告)日：2015-04-14
申请号：US13167133
申请日：2011-06-23
CPC分类号： H01L24/96 , H01L21/561 , H01L21/568 , H01L24/19 , H01L24/20 , H01L24/97 , H01L25/105 , H01L2224/04105 , H01L2224/19 , H01L2224/96 , H01L2224/97 , H01L2225/1035 , H01L2924/00 , H01L2924/01029 , H01L2924/01322 , H01L2924/014 , H01L2924/07802 , H01L2924/12041 , H01L2924/12042 , H01L2924/1306 , H01L2924/13091 , H01L2924/15747 , H01L2924/181 , H01L2924/1815 , H01L2924/00012
摘要： A semiconductor device has a carrier with a die attach area. Recesses are formed partially through the carrier outside the die attach area. A first conductive layer is conformally applied over a surface of the carrier and into the recesses. A semiconductor die is mounted to the die attach area of the carrier. An encapsulant is deposited over the carrier and semiconductor die. The encapsulant extends into the recesses over the first conductive layer to form encapsulant bumps. The carrier is removed to expose the first conductive layer over the encapsulant bumps. A first insulating layer is formed over the semiconductor die with openings to expose contact pads of the semiconductor die. A second conductive layer is formed between the first conductive layer and the contact pads on the semiconductor die. A second insulating layer is formed over the second conductive layer and semiconductor die.
摘要翻译： 半导体器件具有带有裸片附着区域的载体。 凹槽部分地通过载体在芯片附着区域外部形成。 第一导电层保形地施加在载体的表面上并进入凹部。 将半导体管芯安装到载体的管芯附着区域。 封装剂沉积在载体和半导体管芯上。 密封剂延伸到第一导电层上的凹槽中以形成密封剂凸块。 去除载体以将第一导电层暴露在密封剂凸块之上。 在半导体管芯上形成第一绝缘层，具有开口以露出半导体管芯的接触焊盘。 在第一导电层和半导体管芯上的接触焊盘之间形成第二导电层。 在第二导电层和半导体管芯上形成第二绝缘层。
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7.发明授权Semiconductor device and method of forming wafer level multi-row etched lead package 有权半导体器件和晶圆级多行蚀刻引线封装形成方法公开(公告)号：US08241956B2
公开(公告)日：2012-08-14
申请号：US12719476
申请日：2010-03-08
IPC分类号： H01L21/00
CPC分类号： H01L21/56 , H01L23/28 , H01L25/11 , H01L2224/04105 , H01L2224/12105 , H01L2224/24247 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/48091 , H01L2224/48229 , H01L2224/48235 , H01L2224/73265 , H01L2224/73267 , H01L2224/92244 , H01L2924/01322 , H01L2924/13091 , H01L2924/15153 , H01L2924/15311 , H01L2924/181 , H01L2924/18162 , H01L2924/3025 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： A semiconductor device has a base carrier having first and second opposing surfaces. The first surface of the base carrier is etched to form a plurality of cavities and multiple rows of base leads between the cavities extending between the first and second surfaces. A second conductive layer is formed over the second surface of the base carrier. A semiconductor die is mounted within a cavity of the base carrier. A first insulating layer is formed over the die and first surface of the base carrier and into the cavities. A first conductive layer is formed over the first insulating layer and first surface of the base carrier. A second insulating layer is formed over the first insulating layer and first conductive layer. A portion of the second surface of the base carrier is removed to expose the first insulating layer and electrically isolate the base leads.
摘要翻译： 半导体器件具有具有第一和第二相对表面的基底载体。 基底托架的第一表面被蚀刻以形成在第一和第二表面之间延伸的空腔之间的多个空腔和多排基底引线。 第二导电层形成在基底载体的第二表面上。 半导体管芯安装在基座的空腔内。 第一绝缘层形成在基体载体的模具和第一表面上并进入空腔中。 在第一绝缘层和基底载体的第一表面上形成第一导电层。 在第一绝缘层和第一导电层上形成第二绝缘层。 去除基底载体的第二表面的一部分以露出第一绝缘层并电绝缘基极。
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8.发明申请Semiconductor Device and Method of Forming Wafer-Level Multi-Row Etched Leadframe With Base Leads and Embedded Semiconductor Die 有权半导体器件及其基片和嵌入式半导体晶片级晶圆多列蚀刻引线框的形成方法公开(公告)号：US20120038064A1
公开(公告)日：2012-02-16
申请号：US13284811
申请日：2011-10-28
CPC分类号： H01L24/29 , H01L21/4832 , H01L23/49548 , H01L23/49575 , H01L23/49582 , H01L24/16 , H01L24/19 , H01L24/32 , H01L24/48 , H01L24/73 , H01L24/81 , H01L24/85 , H01L24/92 , H01L25/0657 , H01L25/105 , H01L25/16 , H01L25/50 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/16225 , H01L2224/16227 , H01L2224/16245 , H01L2224/29111 , H01L2224/2919 , H01L2224/32014 , H01L2224/32145 , H01L2224/48247 , H01L2224/73253 , H01L2224/73265 , H01L2224/73267 , H01L2224/81191 , H01L2224/81411 , H01L2224/81424 , H01L2224/81439 , H01L2224/81444 , H01L2224/81447 , H01L2224/81455 , H01L2224/83805 , H01L2224/85411 , H01L2224/85424 , H01L2224/85439 , H01L2224/85444 , H01L2224/85447 , H01L2224/85455 , H01L2224/92247 , H01L2225/0651 , H01L2225/06517 , H01L2225/06558 , H01L2225/1023 , H01L2225/1029 , H01L2225/1035 , H01L2225/1052 , H01L2225/1058 , H01L2225/107 , H01L2924/00011 , H01L2924/00014 , H01L2924/01014 , H01L2924/01029 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/0132 , H01L2924/01322 , H01L2924/014 , H01L2924/12041 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/1432 , H01L2924/1433 , H01L2924/14335 , H01L2924/1434 , H01L2924/15311 , H01L2924/1579 , H01L2924/181 , H01L2924/00 , H01L2224/45099 , H01L2924/0105 , H01L2924/01082 , H01L2924/00012 , H01L2224/13111 , H01L2924/0665 , H01L2224/81805
摘要： A semiconductor device has a base substrate with first and second opposing surfaces. A plurality of cavities and base leads between the cavities is formed in the first surface of the base substrate. The first set of base leads can have a different height or similar height as the second set of base leads. A concave capture pad can be formed over the second set of base leads. Alternatively, a plurality of openings can be formed in the base substrate and the semiconductor die mounted to the openings. A semiconductor die is mounted between a first set of the base leads and over a second set of the base leads. An encapsulant is deposited over the die and base substrate. A portion of the second surface of the base substrate is removed to separate the base leads. An interconnect structure is formed over the encapsulant and base leads.
摘要翻译： 半导体器件具有带有第一和第二相对表面的基底基板。 在基底基板的第一表面中形成有在空腔之间的多个空腔和基底引线。 第一组基线可以具有与第二组基线不同的高度或相似的高度。 可以在第二组基线上形成凹形捕获垫。 或者，可以在基底基板和安装到开口的半导体管芯上形成多个开口。 半导体管芯安装在第一组基极引线之间和第二组基极引线之间。 密封剂沉积在管芯和基底衬底上。 去除基底基板的第二表面的一部分以分离基底引线。 在密封剂和基底引线上形成互连结构。
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9.发明授权Semiconductor device and method of forming leadframe interposer over semiconductor die and TSV substrate for vertical electrical interconnect 有权在半导体管芯上形成引线框架插入件的半导体器件和方法以及用于垂直电互连的TSV衬底公开(公告)号：US08409922B2
公开(公告)日：2013-04-02
申请号：US12882110
申请日：2010-09-14
IPC分类号： H01L21/00 , H01L23/495
CPC分类号： H01L23/495 , H01L21/4832 , H01L21/4853 , H01L21/56 , H01L21/563 , H01L23/3107 , H01L23/3128 , H01L23/3135 , H01L23/49811 , H01L23/49816 , H01L23/49827 , H01L24/03 , H01L24/05 , H01L24/16 , H01L24/29 , H01L24/32 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/81 , H01L25/03 , H01L25/0657 , H01L25/105 , H01L2224/0345 , H01L2224/03452 , H01L2224/03462 , H01L2224/03464 , H01L2224/0401 , H01L2224/04042 , H01L2224/05611 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/06131 , H01L2224/16225 , H01L2224/29144 , H01L2224/2919 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48105 , H01L2224/48157 , H01L2224/48175 , H01L2224/48227 , H01L2224/48228 , H01L2224/48247 , H01L2224/49113 , H01L2224/73204 , H01L2224/73253 , H01L2224/73265 , H01L2224/81411 , H01L2224/81424 , H01L2224/81439 , H01L2224/81444 , H01L2224/81447 , H01L2224/81455 , H01L2224/831 , H01L2225/06517 , H01L2225/1023 , H01L2225/1041 , H01L2225/1058 , H01L2924/00011 , H01L2924/00014 , H01L2924/01079 , H01L2924/01322 , H01L2924/12041 , H01L2924/12042 , H01L2924/13091 , H01L2924/14 , H01L2924/15311 , H01L2924/157 , H01L2924/1579 , H01L2924/181 , H01L2924/1815 , H01L2924/3511 , H05K2203/0384 , H01L2924/01014 , H01L2924/0665 , H01L2924/00 , H01L2924/00012 , H01L2224/81805 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor device has a substrate with a plurality of conductive vias formed through the substrate and first conductive layer formed over the substrate. A first semiconductor die is mounted over the substrate. A second semiconductor die can be mounted over the first semiconductor die. A leadframe interposer has a base plate and a plurality of base leads extending from the base plate. An etch-resistant conductive layer is formed over a surface of the base plate opposite the base leads. The leadframe is mounted to the substrate over the first semiconductor die. An encapsulant is deposited over the substrate and first semiconductor die. The base plate is removed while retaining the etch-resistant conductive layer and portion of the base plate opposite the base leads to electrically isolate the base leads. An interconnect structure is formed over a surface of the substrate opposite the base leads.
摘要翻译： 半导体器件具有衬底，其具有通过衬底形成的多个导电通孔和形成在衬底上的第一导电层。 第一半导体管芯安装在衬底上。 第二半导体管芯可以安装在第一半导体管芯上。 引线框架插入件具有基板和从基板延伸的多个基底引线。 在与基极相对的基板的表面上形成耐蚀刻导电层。 引线框架安装在第一半导体管芯上的衬底上。 密封剂沉积在衬底和第一半导体管芯上。 去除基板，同时保持耐蚀刻导电层，并且基板的与基底引线相对的部分电绝缘基极。 在与基极相对的基板的表面上形成互连结构。
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10.发明授权Semiconductor device and method of forming wafer-level multi-row etched leadframe with base leads and embedded semiconductor die 有权用基极引线和嵌入式半导体芯片形成晶圆级多行蚀刻引线框的半导体器件和方法公开(公告)号：US08076184B1
公开(公告)日：2011-12-13
申请号：US12857395
申请日：2010-08-16
CPC分类号： H01L24/29 , H01L21/4832 , H01L23/49548 , H01L23/49575 , H01L23/49582 , H01L24/16 , H01L24/19 , H01L24/32 , H01L24/48 , H01L24/73 , H01L24/81 , H01L24/85 , H01L24/92 , H01L25/0657 , H01L25/105 , H01L25/16 , H01L25/50 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/16225 , H01L2224/16227 , H01L2224/16245 , H01L2224/29111 , H01L2224/2919 , H01L2224/32014 , H01L2224/32145 , H01L2224/48247 , H01L2224/73253 , H01L2224/73265 , H01L2224/73267 , H01L2224/81191 , H01L2224/81411 , H01L2224/81424 , H01L2224/81439 , H01L2224/81444 , H01L2224/81447 , H01L2224/81455 , H01L2224/83805 , H01L2224/85411 , H01L2224/85424 , H01L2224/85439 , H01L2224/85444 , H01L2224/85447 , H01L2224/85455 , H01L2224/92247 , H01L2225/0651 , H01L2225/06517 , H01L2225/06558 , H01L2225/1023 , H01L2225/1029 , H01L2225/1035 , H01L2225/1052 , H01L2225/1058 , H01L2225/107 , H01L2924/00011 , H01L2924/00014 , H01L2924/01014 , H01L2924/01029 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/0132 , H01L2924/01322 , H01L2924/014 , H01L2924/12041 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/1432 , H01L2924/1433 , H01L2924/14335 , H01L2924/1434 , H01L2924/15311 , H01L2924/1579 , H01L2924/181 , H01L2924/00 , H01L2224/45099 , H01L2924/0105 , H01L2924/01082 , H01L2924/00012 , H01L2224/13111 , H01L2924/0665 , H01L2224/81805
摘要： A semiconductor device has a base carrier with first and second opposing surfaces. A plurality of cavities and base leads between the cavities is formed in the first surface of the base carrier. The first set of base leads can have a different height or similar height as the second set of base leads. A concave capture pad can be formed over the second set of base leads. Alternatively, a plurality of openings can be formed in the base carrier and the semiconductor die mounted to the openings. A semiconductor die is mounted between a first set of the base leads and over a second set of the base leads. An encapsulant is deposited over the die and base carrier. A portion of the second surface of the base carrier is removed to separate the base leads. An interconnect structure is formed over the encapsulant and base leads.
摘要翻译： 半导体器件具有带有第一和第二相对表面的基底载体。 在基座的第一表面中形成有空腔之间的多个空腔和底座引线。 第一组基线可以具有与第二组基线不同的高度或相似的高度。 可以在第二组基线上形成凹形捕获垫。 或者，可以在基座载体和安装到开口的半导体管芯上形成多个开口。 半导体管芯安装在第一组基极引线之间和第二组基极引线之间。 密封剂沉积在管芯和基底载体上。 移除基底载体的第二表面的一部分以分离基底引线。 在密封剂和基底引线上形成互连结构。
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