公开(公告)号：US06586322B1

公开(公告)日：2003-07-01

申请号：US10032341

申请日：2001-12-21

申请人： Chih-Cheng Chiu ,  Sheng-Liang Pan ,  Kuo-Liang Lu

发明人： Chih-Cheng Chiu ,  Sheng-Liang Pan ,  Kuo-Liang Lu

IPC分类号： H01L2144

CPC分类号： H01L24/11 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/03462 ,  H01L2224/0347 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05027 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05655 ,  H01L2224/1147 ,  H01L2224/11474 ,  H01L2224/11849 ,  H01L2224/11902 ,  H01L2224/11914 ,  H01L2224/13023 ,  H01L2224/13111 ,  H01L2924/00013 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/0105 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2224/05099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/29099 ,  H01L2224/29599

摘要： A method of forming a bump on a substrate such as a semiconductor wafer or flip chip. The method includes the step of providing a semiconductor device having a contact pad and an upper passivation layer and an opening formed in the upper passivation layer exposing a portion of the contact pad. An under bump metallurgy is deposited over the upper passivation layer and the contact pad. A first photoresist layer is deposited in a liquid state so that the first photoresist layer covers the under bump metallurgy. A second photoresist layer is deposited and the second photoresist layer is a dry film photoresist. The unexposed portions of the first photoresist layer are removed. The remaining portions of the first photoresist layers are removed. The electrically conductive material is reflown to provide a bump on the semiconductor device.

摘要翻译： 在半导体晶片或倒装芯片等基板上形成凸点的方法。 该方法包括提供具有接触焊盘和上钝化层的半导体器件的步骤，以及形成在上钝化层中的开口，露出接触焊盘的一部分。 在上钝化层和接触焊盘上沉积凸块下冶金。 以液态沉积第一光致抗蚀剂层，使得第一光致抗蚀剂层覆盖凸块下金属。 沉积第二光致抗蚀剂层，第二光致抗蚀剂层是干膜光致抗蚀剂。 去除第一光致抗蚀剂层的未曝光部分。 去除第一光致抗蚀剂层的剩余部分。 导电材料被重熔以在半导体器件上提供凸块。

公开(公告)号：US09263390B2

公开(公告)日：2016-02-16

申请号：US13889582

申请日：2013-05-08

申请人： Semiconductor Components Industries, LLC

发明人： Michael J. Seddon ,  Francis J. Carney

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/532 ,  H01L23/00 ,  H01L23/58 ,  H01L21/768 ,  H01L23/31

CPC分类号： H01L23/53238 ,  H01L21/76885 ,  H01L23/3157 ,  H01L23/53252 ,  H01L23/58 ,  H01L24/03 ,  H01L24/05 ,  H01L24/10 ,  H01L24/11 ,  H01L24/13 ,  H01L24/48 ,  H01L2224/02126 ,  H01L2224/0345 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05027 ,  H01L2224/05166 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/11472 ,  H01L2224/11474 ,  H01L2224/11906 ,  H01L2224/11914 ,  H01L2224/13007 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13562 ,  H01L2224/13582 ,  H01L2224/13583 ,  H01L2224/13584 ,  H01L2224/136 ,  H01L2224/13611 ,  H01L2224/13644 ,  H01L2224/13647 ,  H01L2224/13655 ,  H01L2224/13664 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2224/05552 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： In accordance with an embodiment a semiconductor component includes an electrically conductive structure formed over a portion of a semiconductor material. An electrical interconnect having a top surface and opposing edges contacts the electrically conductive structure. A protective structure is formed on the top surface and the opposing edges of the electrical interconnect and over a portion of the electrically conductive structure, wherein the protective structure forms a seal that protects the electrical interconnect.

公开(公告)号：US09219010B2

公开(公告)日：2015-12-22

申请号：US13889573

申请日：2013-05-08

申请人： Semiconductor Components Industries, LLC

发明人： Michael J. Seddon ,  Francis J. Carney

IPC分类号： H01L21/44 ,  H01L21/768 ,  H01L23/00 ,  H01L23/58 ,  H01L23/31

CPC分类号： H01L23/53238 ,  H01L21/76885 ,  H01L23/3157 ,  H01L23/53252 ,  H01L23/58 ,  H01L24/03 ,  H01L24/05 ,  H01L24/10 ,  H01L24/11 ,  H01L24/13 ,  H01L24/48 ,  H01L2224/02126 ,  H01L2224/0345 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05027 ,  H01L2224/05166 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/11472 ,  H01L2224/11474 ,  H01L2224/11906 ,  H01L2224/11914 ,  H01L2224/13007 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13562 ,  H01L2224/13582 ,  H01L2224/13583 ,  H01L2224/13584 ,  H01L2224/136 ,  H01L2224/13611 ,  H01L2224/13644 ,  H01L2224/13647 ,  H01L2224/13655 ,  H01L2224/13664 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2224/05552 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A method for manufacturing a semiconductor component that includes the use of multiple layers of photoresist. A first layer of electrically conductive material is formed over a substrate and a first layer of photoresist is formed over the first layer of electrically conductive material. A portion of the first layer of photoresist is removed leaving photoresist having sidewalls separated by a gap. A second layer of electrically conductive material having first and second sidewalls is formed in the gap. A second layer of photoresist is formed over the first layer of photoresist and over the second layer of electrically conductive material. Portions of the second layer of photoresist and the first layer of photoresist are removed to uncover the first and second edges of the second layer of electrically conductive material. A protective structure is formed over the first and second edges of the second electrically conductive material.

摘要翻译： 一种制造半导体元件的方法，包括使用多层光致抗蚀剂。 第一层导电材料形成在衬底上，第一层光致抗蚀剂形成在第一层导电材料上。 除去第一层光致抗蚀剂的一部分，留下具有通过间隙分隔的侧壁的光致抗蚀剂。 具有第一和第二侧壁的第二层导电材料形成在间隙中。 第二层光致抗蚀剂形成在第一层光致抗蚀剂上方和第二层导电材料上。 去除第二层光致抗蚀剂和第一层光致抗蚀剂的部分以露出第二层导电材料的第一和第二边缘。 在第二导电材料的第一和第二边缘上形成保护结构。

公开(公告)号：US08692367B1

公开(公告)日：2014-04-08

申请号：US13633108

申请日：2012-10-01

申请人： Maxim Integrated Products, Inc.

发明人： Chiung C. Lo ,  Arkadii V. Samoilov ,  Reynante T. Alvarado

IPC分类号： H01L23/48

CPC分类号： H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/64 ,  H01L24/66 ,  H01L24/69 ,  H01L24/81 ,  H01L24/89 ,  H01L2224/0401 ,  H01L2224/06102 ,  H01L2224/11914 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/1403 ,  H01L2224/81136 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/83191 ,  H01L2224/83194 ,  H01L2224/83907 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01068 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/3025

摘要： A wafer-level packaged semiconductor device is described. In an implementation, the device includes one or more self-assembled resilient leads disposed on an integrated circuit chip. Each of the resilient leads are configured to move from a first position wherein the resilient lead is held adjacent to the chip and a second position wherein the resilient lead is extended away from the chip to interconnect the chip to a printed circuit board. A guard is provided to protect the resilient leads when the resilient leads are in the first position. One or more attachment bumps may also be furnished to facilitate attachment of the device to the printed circuit board.

摘要翻译： 描述了晶片级封装半导体器件。 在一个实现中，该装置包括设置在集成电路芯片上的一个或多个自组装的弹性引线。 每个弹性引线构造成从第一位置移动，其中弹性引线邻近芯片保持，第二位置，其中弹性引线远离芯片延伸以将芯片与印刷电路板互连。 当弹性引线处于第一位置时，提供防护件以保护弹性引线。 还可以设置一个或多个附接凸块以便于将装置附接到印刷电路板。

公开(公告)号：US09159684B1

公开(公告)日：2015-10-13

申请号：US14246394

申请日：2014-04-07

申请人： Maxim Integrated Products, Inc.

发明人： Chiung C. Lo ,  Arkadii V. Samoilov ,  Reynante Alvarado

IPC分类号： H01L23/00

CPC分类号： H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/64 ,  H01L24/66 ,  H01L24/69 ,  H01L24/81 ,  H01L24/89 ,  H01L2224/0401 ,  H01L2224/06102 ,  H01L2224/11914 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/1403 ,  H01L2224/81136 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/83191 ,  H01L2224/83194 ,  H01L2224/83907 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01068 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/3025

摘要： A wafer-level packaged semiconductor device is described. In an implementation, the device includes one or more self-assembled resilient leads disposed on an integrated circuit chip. Each of the resilient leads are configured to move from a first position wherein the resilient lead is held adjacent to the chip and a second position wherein the resilient lead is extended away from the chip to interconnect the chip to a printed circuit board. A guard is provided to protect the resilient leads when the resilient leads are in the first position. One or more attachment bumps may also be furnished to facilitate attachment of the device to the printed circuit board.

摘要翻译： 描述了晶片级封装半导体器件。 在一个实现中，该装置包括设置在集成电路芯片上的一个或多个自组装的弹性引线。 每个弹性引线构造成从第一位置移动，其中弹性引线邻近芯片保持，第二位置，其中弹性引线远离芯片延伸以将芯片与印刷电路板互连。 当弹性引线处于第一位置时，提供防护件以保护弹性引线。 还可以设置一个或多个附接凸块以便于将装置附接到印刷电路板。

公开(公告)号：US08278748B2

公开(公告)日：2012-10-02

申请号：US12707239

申请日：2010-02-17

申请人： Chiung C. Lo ,  Arkadii V. Samoilov ,  Reynante Alvarado

发明人： Chiung C. Lo ,  Arkadii V. Samoilov ,  Reynante Alvarado

IPC分类号： H01L23/52

CPC分类号： H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/64 ,  H01L24/66 ,  H01L24/69 ,  H01L24/81 ,  H01L24/89 ,  H01L2224/0401 ,  H01L2224/06102 ,  H01L2224/11914 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/1403 ,  H01L2224/81136 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/83191 ,  H01L2224/83194 ,  H01L2224/83907 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01068 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/3025

摘要： A wafer-level packaged semiconductor device is described. In an implementation, the device includes one or more self-assembled resilient leads disposed on an integrated circuit chip. Each of the resilient leads are configured to move from a first position wherein the resilient lead is held adjacent to the chip and a second position wherein the resilient lead is extended away from the chip to interconnect the chip to a printed circuit board. A guard is provided to protect the resilient leads when the resilient leads are in the first position. One or more attachment bumps may also be furnished to facilitate attachment of the device to the printed circuit board.

摘要翻译： 描述了晶片级封装半导体器件。 在一个实现中，该装置包括设置在集成电路芯片上的一个或多个自组装的弹性引线。 每个弹性引线构造成从第一位置移动，其中弹性引线邻近芯片保持，第二位置，其中弹性引线远离芯片延伸以将芯片与印刷电路板互连。 当弹性引线处于第一位置时，提供防护件以保护弹性引线。 还可以设置一个或多个附接凸块以便于将装置附接到印刷电路板。

公开(公告)号：US07871857B1

公开(公告)日：2011-01-18

申请号：US12240292

申请日：2008-09-29

申请人： Kuolung Lei ,  Harmeet Bhugra

发明人： Kuolung Lei ,  Harmeet Bhugra

IPC分类号： H01L21/00 ,  H01L23/02 ,  H05K1/14

CPC分类号： H01L21/78 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/94 ,  H01L24/97 ,  H01L25/50 ,  H01L2224/03462 ,  H01L2224/0347 ,  H01L2224/0401 ,  H01L2224/051 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/11462 ,  H01L2224/11901 ,  H01L2224/11914 ,  H01L2224/13011 ,  H01L2224/13082 ,  H01L2224/13101 ,  H01L2224/13117 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/81097 ,  H01L2224/81141 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2224/81899 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2924/00

摘要： Methods of forming multi-chip semiconductor substrates include forming a first plurality of dicing streets in a first surface of a first semiconductor wafer having a first plurality of bonding sites thereon and forming a second plurality of dicing streets in a first surface of a second semiconductor wafer having a second plurality of bonding sites thereon. The first surfaces of the first and second semiconductor wafers are bonded together so that the first plurality of dicing streets are aligned with the second plurality of dicing streets and the first plurality of bonding sites are matingly received and permanently affixed within the second plurality of bonding sites. A plurality of bonded pairs of semiconductor chips are then formed by planarizing the second surface of the second semiconductor wafer until the second plurality of dicing streets are exposed.

摘要翻译： 形成多芯片半导体衬底的方法包括在其上具有第一多个结合位置的第一半导体晶片的第一表面中形成第一多个切割街道，并且在第二半导体晶片的第一表面中形成第二多个切割街道 在其上具有第二多个结合位置。 第一和第二半导体晶片的第一表面被结合在一起，使得第一多个切割街道与第二多个切割街道对准，并且第一多个结合位置被配合地接收并永久地固定在第二多个结合位置 。 然后通过平面化第二半导体晶片的第二表面直到第二多个切割街道露出来形成多个键合的半导体芯片对。

公开(公告)号：US08937009B2

公开(公告)日：2015-01-20

申请号：US13870026

申请日：2013-04-25

申请人： International Business Machines Corporation

发明人： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Karen P. McLaughlin ,  Ekta Misra ,  Christopher D. Muzzy ,  Eric D. Perfecto ,  Wolfgang Sauter

IPC分类号： H01L21/768 ,  H01L21/44 ,  H01L23/498 ,  H01L23/00

CPC分类号： H01L24/11 ,  H01L22/34 ,  H01L23/3192 ,  H01L23/585 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L2224/03462 ,  H01L2224/03622 ,  H01L2224/03914 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05082 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05558 ,  H01L2224/05568 ,  H01L2224/05583 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/06135 ,  H01L2224/06136 ,  H01L2224/11462 ,  H01L2224/11622 ,  H01L2224/11849 ,  H01L2224/11914 ,  H01L2224/13023 ,  H01L2224/13026 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13118 ,  H01L2224/1312 ,  H01L2224/13147 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/1305 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/00 ,  H01L2224/05552

摘要： Disclosed are a method for metallization during semiconductor wafer processing and the resulting structures. In this method, a passivation layer is patterned with first openings aligned above and extending vertically to metal structures below. A mask layer is formed and patterned with second openings aligned above the first openings, thereby forming two-tier openings extending vertically through the mask layer and passivation layer to the metal structures below. An electrodeposition process forms, in the two-tier openings, both under-bump pad(s) and additional metal feature(s), which are different from the under-bump pad(s) (e.g., a wirebond pad; a final vertical section of a crackstop structure; and/or a probe pad). Each under-bump pad and additional metal feature initially comprises copper with metal cap layers thereon. The mask layer is removed, an additional mask layer is formed and patterned with third opening(s) exposing only the under-bump pad(s) and solder material is deposited on the under-bump pad(s).

摘要翻译： 公开了半导体晶片处理期间的金属化方法和所得到的结构。 在该方法中，钝化层被图案化，其中第一开口在上方对齐并垂直延伸到下面的金属结构。 形成掩模层并用第一开口对准的第二开口进行图案化，从而形成垂直延伸穿过掩模层和钝化层到下面的金属结构的两层开口。 电沉积工艺在双层开口中形成凸点下焊盘和附加的金属部件，其不同于凸块下焊盘（例如，引线焊盘;最终垂直的） 裂缝结构部分和/或探针垫）。 每个凸点下焊盘和附加的金属特征最初包括铜上的金属盖层。 去除掩模层，形成另外的掩模层并用仅暴露凸块下焊盘的第三开口图案化，并且焊料材料沉积在凸块下焊盘上。

公开(公告)号：US08445375B2

公开(公告)日：2013-05-21

申请号：US12569732

申请日：2009-09-29

申请人： Michael J. Seddon ,  Francis J. Carney

发明人： Michael J. Seddon ,  Francis J. Carney

IPC分类号： H01L21/44

CPC分类号： H01L23/53238 ,  H01L21/76885 ,  H01L23/3157 ,  H01L23/53252 ,  H01L23/58 ,  H01L24/03 ,  H01L24/05 ,  H01L24/10 ,  H01L24/11 ,  H01L24/13 ,  H01L24/48 ,  H01L2224/02126 ,  H01L2224/0345 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05027 ,  H01L2224/05166 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/11472 ,  H01L2224/11474 ,  H01L2224/11906 ,  H01L2224/11914 ,  H01L2224/13007 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13562 ,  H01L2224/13582 ,  H01L2224/13583 ,  H01L2224/13584 ,  H01L2224/136 ,  H01L2224/13611 ,  H01L2224/13644 ,  H01L2224/13647 ,  H01L2224/13655 ,  H01L2224/13664 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2224/05552 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor component and methods for manufacturing the semiconductor component that includes a double exposure of a layer of photoresist or the use of multiple layers of photoresist. A metallization structure is formed on a layer of electrically conductive material that is disposed on a substrate and a layer of photoresist is formed on the metallization structure. The layer of photoresist is exposed to light and developed to remove a portion of the photoresist layer, thereby forming an opening. Then, a larger portion of the photoresist layer is exposed to light and an electrically conductive interconnect is formed in the opening. The larger portion of the photoresist layer that was exposed to light is developed to expose edges of the electrically conductive interconnect and portions of the metallization structure. A protection layer is formed on the top and edges of the electrically conductive interconnect and on the exposed portions of the metallization structure.

摘要翻译： 一种半导体部件和用于制造半导体部件的方法，包括光致抗蚀剂层的双重曝光或多层光致抗蚀剂的使用。 金属化结构形成在导电材料层上，该导电材料层设置在基板上，并且在金属化结构上形成光刻胶层。 将光致抗蚀剂层暴露于光并显影以除去光致抗蚀剂层的一部分，从而形成开口。 然后，光致抗蚀剂层的较大部分暴露于光，并且在开口中形成导电互连。 显影光致抗蚀剂层的较大部分被曝光以暴露导电互连件的边缘和金属化结构的部分。 在导电互连的顶部和边缘以及金属化结构的暴露部分上形成保护层。

公开(公告)号：US20110198745A1

公开(公告)日：2011-08-18

申请号：US12707239

申请日：2010-02-17

申请人： Chiung C. Lo ,  Arkadii V. Samoilov ,  Reynante T. Alvarado

发明人： Chiung C. Lo ,  Arkadii V. Samoilov ,  Reynante T. Alvarado

IPC分类号： H01L23/498 ,  H01L21/78

CPC分类号： H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/64 ,  H01L24/66 ,  H01L24/69 ,  H01L24/81 ,  H01L24/89 ,  H01L2224/0401 ,  H01L2224/06102 ,  H01L2224/11914 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/1403 ,  H01L2224/81136 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/83191 ,  H01L2224/83194 ,  H01L2224/83907 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01068 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/3025

摘要： A wafer-level packaged semiconductor device is described. In an implementation, the device includes one or more self-assembled resilient leads disposed on an integrated circuit chip. Each of the resilient leads are configured to move from a first position wherein the resilient lead is held adjacent to the chip and a second position wherein the resilient lead is extended away from the chip to interconnect the chip to a printed circuit board. A guard is provided to protect the resilient leads when the resilient leads are in the first position. One or more attachment bumps may also be furnished to facilitate attachment of the device to the printed circuit board.

摘要翻译： 描述了晶片级封装半导体器件。 在一个实现中，该装置包括设置在集成电路芯片上的一个或多个自组装的弹性引线。 每个弹性引线构造成从第一位置移动，其中弹性引线邻近芯片保持，第二位置，其中弹性引线远离芯片延伸以将芯片与印刷电路板互连。 当弹性引线处于第一位置时，提供防护件以保护弹性引线。 还可以设置一个或多个附接凸块以便于将装置附接到印刷电路板。