公开(公告)号：US20240313780A1

公开(公告)日：2024-09-19

申请号：US18182996

申请日：2023-03-13

申请人： PARADE TECHNOLOGIES, LTD

发明人： Chieh-Yuan Chao ,  Jenghung Tsai

IPC分类号： H03K19/173 ,  H03K17/693 ,  H03K19/003 ,  H03K19/1776

CPC分类号： H03K19/1737 ,  H03K17/693 ,  H03K19/00361 ,  H03K19/1776

摘要： An electronic device includes two multiplexer branches, a modulation circuit, and an output interface coupled to the modulation circuit and two multiplexer branches. A first multiplexer branch generate s first output signal from a first selection signal, a first inverse signal, and a first input signal. The first inverse signal is substantially complementary to the first selection signal. A second multiplexer branch generates a second output signal from the first selection signal, the first inverse signal, and a second input signal. The modulation circuit generates a logic output signal from the first input signal and the second input signal, independently of the first selection signal and the first inverse signal. The output interface generates a multiplexed signal tracking one of the first input signal and the second input signal based on the first output signal, the second output signal, and the logic output signal.

公开(公告)号：US12057837B2

公开(公告)日：2024-08-06

申请号：US17485226

申请日：2021-09-24

申请人： iCometrue Company Ltd.

发明人： Jin-Yuan Lee ,  Mou-Shiung Lin

IPC分类号： H03K19/1776 ,  G11C11/16 ,  G11C11/412 ,  G11C11/419 ,  G11C13/00 ,  G11C14/00 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L25/18 ,  H03K19/0948 ,  H03K19/173 ,  H03K19/17728 ,  H03K19/20 ,  H10B10/00 ,  H10B61/00 ,  H10B63/00 ,  H10N70/00 ,  H03K19/21

CPC分类号： H03K19/1776 ,  G11C11/1673 ,  G11C11/412 ,  G11C11/419 ,  G11C13/0007 ,  G11C13/0038 ,  G11C13/004 ,  G11C14/0081 ,  G11C14/009 ,  H01L23/49811 ,  H01L23/5386 ,  H01L24/13 ,  H01L24/16 ,  H01L25/18 ,  H03K19/0948 ,  H03K19/1737 ,  H03K19/17728 ,  H03K19/20 ,  H10B10/00 ,  H10B10/15 ,  H10B61/00 ,  H10B61/10 ,  H10B63/00 ,  H10B63/20 ,  H10B63/30 ,  H10B63/80 ,  H10N70/826 ,  H10N70/841 ,  H10N70/8833 ,  G11C2213/15 ,  H01L2224/13023 ,  H01L2224/13024 ,  H01L2224/13082 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/81191 ,  H01L2224/81447 ,  H01L2224/83104 ,  H01L2224/92225 ,  H01L2224/97 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1443 ,  H03K19/21 ,  H01L2224/97 ,  H01L2224/81 ,  H01L2224/83104 ,  H01L2924/00014 ,  H01L2224/81447 ,  H01L2924/00014

摘要： A field-programmable-gate-array (FPGA) integrated-circuit (IC) chip configured to perform a logic function based on a look-up table (LUT), includes: multiple non-volatile memory cells therein configured to store multiple resulting values of the look-up table (LUT); and a programmable logic block therein having multiple static-random-access-memory (SRAM) cells configured to store the resulting values passed from the non-volatile memory cells, wherein the programmable logic block is configured to select, in accordance with one of the combinations of its inputs, one from the resulting values stored in the static-random-access-memory (SRAM) cells into its output.

公开(公告)号：US12047070B2

公开(公告)日：2024-07-23

申请号：US17849733

申请日：2022-06-27

申请人： Wiwynn Corporation

发明人： Wei-Fang Chang ,  Yu-Chun Chen ,  Nan-Huan Lin ,  Chung-Hui Yen ,  Shi-Rui Chen

IPC分类号： G06F13/40 ,  H03K19/017 ,  H03K19/17736 ,  H03K19/1776 ,  H03K19/17784 ,  H03K19/20

CPC分类号： H03K19/1776 ,  G06F13/4081 ,  H03K19/01742 ,  H03K19/1774 ,  H03K19/17784 ,  H03K19/20

摘要： A main board, a hot plug control signal generator, and a control signal generating method thereof are provided. The hot plug control signal generator includes a controller and a latch. The controller provides a control signal. The latch is operated based on an operation power to generate a hot plug control signal. The latch sets the hot plug control signal to a disabled first logic value, and latches the hot plug control signal at the first logic value.

公开(公告)号：US20240204782A1

公开(公告)日：2024-06-20

申请号：US18081907

申请日：2022-12-15

申请人： Intel Corporation

发明人： Amit Agarwal ,  Steven K. Hsu ,  Ram Kumar Krishnamurthy

IPC分类号： H03K19/094 ,  H03K19/017 ,  H03K19/1776

CPC分类号： H03K19/09425 ,  H03K19/01728 ,  H03K19/1776

摘要： Some embodiments include an apparatus having a flip-flop circuit, which can include a first tristate inverter, a second tristate inverter including an input node coupled to an input node of the first tristate inverter; a first additional inverter including, and a second additional inverter including an output node coupled to an output node of the first additional inverter; a first memory including a first memory node coupled to an output node of the second tristate inverter, and a first additional memory node coupled to an input node of the first additional inverter; and a second memory including a second memory node coupled to an output node of the first tristate inverter, and a second additional memory node coupled to an input node of the second additional inverter.

公开(公告)号：US11984889B2

公开(公告)日：2024-05-14

申请号：US17833970

申请日：2022-06-07

申请人： Nuvoton Technology Corporation

发明人： Yun-Kai Lai

IPC分类号： H03M1/66 ,  H03K19/17736 ,  H03K19/1776 ,  H03K19/17764 ,  H03K19/17772 ,  H03M1/80

CPC分类号： H03K19/17764 ,  H03K19/1774 ,  H03K19/1776 ,  H03K19/17772 ,  H03M1/808

摘要： A signal generation circuit including a first control circuit, a second control circuit, an arbiter circuit, and a digital-to-analog converter (DAC) circuit is provided. The first control circuit stores a first string of data. The first control circuit enables a first trigger signal in response to a first event occurring. The second control circuit stores a second string of data. The second control circuit enables a second trigger signal in response to a second event occurring. The arbiter circuit reads the first or second control circuit according to the order of priority to use the first string of data or the second string of data as a digital input in response to the first and second trigger signals being enabled. The DAC circuit converts the digital input to generate an analog output.

公开(公告)号：US11973500B2

公开(公告)日：2024-04-30

申请号：US17696473

申请日：2022-03-16

申请人： Crossbar, Inc.

发明人： Sang Nguyen ,  Cung Vu ,  Hagop Nazarian

IPC分类号： H03K19/177 ,  G11C13/00 ,  H03K19/17736 ,  H03K19/17758 ,  H03K19/1776

CPC分类号： H03K19/1776 ,  G11C13/0002 ,  G11C13/0069 ,  G11C13/0097 ,  H03K19/17744 ,  H03K19/17758

摘要： A field programmable gate array (FPGA) utilizing resistive switching memory technology is described. The FPGA can comprise a switching block interconnect having a set of signal input lines and a set of signal output lines. Respective intersections of the signal input lines and signal output lines can have two resistive switching memory cells, a current differential latch, and a switching transistor (also referred to as a pass gate transistor) arranged in a circuit. Resistance states of the resistive switching memory cells can be programmed to control an output voltage state of the current differential latch. The output voltage state is latched into the current differential latch which can drive a gate of the switching transistor to activate or deactivate the switching transistor, which in turn activates or deactivates an intersection of the FPGA.

公开(公告)号：US11942184B2

公开(公告)日：2024-03-26

申请号：US17334811

申请日：2021-05-31

申请人： FUJIFILM Business Innovation Corp.

发明人： Hiroaki Shiokawa

IPC分类号： G11C7/22 ,  G11C7/10 ,  H03K19/1776 ,  H03K19/20

CPC分类号： G11C7/222 ,  G11C7/1051 ,  G11C7/1078 ,  H03K19/1776 ,  H03K19/20

摘要： A programmable logic circuit includes multiple logic blocks that are connected communicatively, wherein multiple modules are reconfigured in any of the logic blocks, and wherein the modules include a first module that is being executed and a second module that is not being executed, and start of execution of the second module is delayed from a start time point of execution of the first module so as to obtain a state in which a first time at which the first module accesses a memory does not overlap a second time at which the second module accesses the memory.

公开(公告)号：US11916552B2

公开(公告)日：2024-02-27

申请号：US17690845

申请日：2022-03-09

申请人： XILINX, INC.

发明人： Ellery Cochell ,  Ripduman Singh Sohan ,  Kieran Mansley

IPC分类号： H03K19/1776 ,  H03K19/17756 ,  G06F30/34 ,  H03K19/00

CPC分类号： H03K19/1776 ,  G06F30/34 ,  H03K19/17756 ,  H03K19/00

摘要： Techniques and apparatus for dynamically modifying a kernel (and associated user-specified circuitry) for a dynamic region of a programmable integrated circuit (IC) without affecting (e.g., while allowing) operation of other kernels ((and other associated user-specified circuitry) in the programmable IC. Dynamically modifying a kernel may include, for example, unloading an existing kernel, loading a new kernel, or replacing a first kernel with a second kernel). In the case of networking (e.g., in a data center application) where the programmable IC may be part of a hardware acceleration card (e.g., a network interface card (NIC)), the kernel may be user code referred to as a “plugin.”

公开(公告)号：US11874788B1

公开(公告)日：2024-01-16

申请号：US17848725

申请日：2022-06-24

申请人： Cadence Design Systems, Inc.

发明人： Vinod Kumar

IPC分类号： G06F13/40 ,  H03K19/1776 ,  H03K19/017 ,  G06F13/16

CPC分类号： G06F13/4072 ,  G06F13/1689 ,  H03K19/01742 ,  H03K19/1776

摘要： Embodiments included herein are directed towards a transmitter circuit. The circuit may include a most significant bit (“MSB”) main driver and a most significant bit boost driver operatively connected to the MSB main driver. The circuit may also include a least significant bit (“LSB”) main driver and a least significant bit boost driver operatively connected to the LSB main driver, wherein the MSB main driver and the LSB main driver are configured to receive two parallel non-return-to-zero (“NRZ”) data inputs.

公开(公告)号：US11874768B1

公开(公告)日：2024-01-16

申请号：US16684477

申请日：2019-11-14

申请人： XILINX, INC.

发明人： Daniel Steger

IPC分类号： G06F12/02 ,  G06F12/10 ,  H03K19/177 ,  H03K19/1776 ,  H03K19/17736

CPC分类号： G06F12/0246 ,  G06F12/10 ,  H03K19/1776 ,  H03K19/17744

摘要： Disclosed approaches for emulating flash memory include storage circuits having respective address decoders. An input-output circuit has pins compatible with a flash memory device and is configured to input flash commands and output response signals via pins. An emulator circuit is configured to translate each flash command into one or more storage-circuit commands compatible with one storage circuit of the storage circuits, and to generate response signals compatible with the flash memory device. A translator circuit is configured to map a flash memory address in each flash command to an address of the one storage circuit, and to transmit the one or more storage-circuit commands and address to the one storage circuit.