公开(公告)号：WO2009023283A2

公开(公告)日：2009-02-19

申请号：PCT/US2008009840

申请日：2008-08-15

Applicant: TESSERA INC ,  KWON JINSU ,  ENDO KIMITAKA ,  MORAN SEAN

Inventor： KWON JINSU ,  ENDO KIMITAKA ,  MORAN SEAN

IPC: H01L23/48

CPC classification number: H05K1/11 ,  H01L21/4853 ,  H01L21/6835 ,  H01L23/498 ,  H01L23/49811 ,  H01L23/49822 ,  H01L24/05 ,  H01L24/16 ,  H01L2221/68345 ,  H01L2224/0401 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/181 ,  H05K3/205 ,  H05K3/4007 ,  H05K3/4644 ,  H05K2201/0367 ,  H05K2203/0384 ,  Y10T29/49124 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T29/49204 ,  H01L2924/00

Abstract: An interconnection element (170, 190) is provided for conductive interconnection with another element (172) having at least one of microelectronic devices or wiring thereon. The interconnection element includes a dielectric element (187) having a major surface. A plated metal layer (130, 192) including a plurality of exposed metal posts (130) can project outwardly beyond the major surface (176) of the dielectric element. Some of the metal posts can be electrically insulated from each other by the dielectric element (187). The interconnection element typically includes a plurality of terminals (151) in conductive communication with the metal posts. The terminals can be connected through the dielectric element (187) to the metal posts (130). The posts may be defined by plating a metal (122, 124) onto exposed co-planar surfaces of a mandrel (120) and interior surfaces of openings (102) in a mandrel, after which the mandrel can be removed.

Abstract translation: 提供互连元件（170,190）用于与具有至少一个微电子器件或其上的布线的另一元件（172）导电互连。 互连元件包括具有主表面的电介质元件（187）。 包括多个暴露的金属柱（130）的镀金属层（130,192）可以向外突出超过介电元件的主表面（176）。 一些金属柱可以通过介电元件（187）彼此电绝缘。 互连元件通常包括与金属柱导电连通的多个端子（151）。 端子可以通过介电元件（187）连接到金属柱（130）。 可以通过将金属（122,124）镀到心轴（120）的暴露的共面表面和心轴中的开口（102）的内表面上来限定所述柱，之后可以移除心轴。

公开(公告)号：WO2009011752A2

公开(公告)日：2009-01-22

申请号：PCT/US2008/008134

申请日：2008-06-27

Applicant: TESSERA, INC. ,  HABA, Belgacem

Inventor： HABA, Belgacem

IPC: H01L23/28

CPC classification number: H01L23/49827 ,  H01L21/486 ,  H01L23/13 ,  H01L23/49861 ,  H01L24/16 ,  H01L24/28 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2224/27013 ,  H01L2224/32057 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48237 ,  H01L2224/4824 ,  H01L2224/484 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/83051 ,  H01L2224/83385 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/078 ,  H01L2924/15151 ,  H01L2924/181 ,  H01L2924/19042 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: Microelectronic package elements (202) and packages (280) having dielectric layers (220) and methods (100) of fabricating such elements (202) and packages (280) are disclosed. The elements (202) and packages (280) may advantageously be used in microelectronic assemblies having high routing density.

Abstract translation: 公开了具有制造这种元件（202）和封装（280）的电介质层（220）和方法（100）的微电子封装元件（202）和封装（280）。 元件（202）和封装（280）可有利地用于具有高布线密度的微电子组件中。

公开(公告)号：WO2008021575A3

公开(公告)日：2008-07-10

申请号：PCT/US2007018521

申请日：2007-08-16

Applicant: TESSERA INC ,  MOHAMMED ILYAS ,  HABA BELGACEM ,  MORAN SEAN ,  WANG WEI-SHUN ,  CHAU ELLIS ,  WADE CHRISTOPHER

Inventor： MOHAMMED ILYAS ,  HABA BELGACEM ,  MORAN SEAN ,  WANG WEI-SHUN ,  CHAU ELLIS ,  WADE CHRISTOPHER

IPC: H01L25/065 ,  H01L23/31 ,  H01L25/10

CPC classification number: H01L25/105 ,  H01L23/3121 ,  H01L23/3157 ,  H01L23/49811 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/06135 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45139 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/49 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2225/06582 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2924/00011

Abstract: A microelectronic package includes a lower unit 11 OA having a lower unit substrate with conductive features and a top and bottom surface 64, 66. The lower unit IIOA includes., one or more lower unit chips 112A, 132A overlying the top surface 64 of the' lower unit substrate 62 that are electrically connected to the conductive features 68, 70 of the lower unit substrate 62. The microelectronic package also includes an upper unit 110 including an upper unit substrate having conductive features, top and bottom surfaces and a hole extending between such top and bottom surfaces. The upper unit further includes one or more upper unit chips 112, 132 overlying the top surface of the upper unit substrate and electrically connected to the conductive features of the upper unit substrate by connections extending within the hole 76.

Abstract translation: 微电子封装包括具有导电特征的下部单元基板和顶部和底部表面64,66的下部单元110A。下部单元IIOA包括一个或多个下部单元芯片112A，132A，其位于 下部单元基板62电连接到下部单元基板62的导电特征68,70。微电子封装还包括上部单元110，上部单元110包括具有导电特征的上部单元基板，顶部和底部表面以及在 这样的顶面和底面。 上部单元还包括一个或多个上部单元芯片112,132，其覆盖在上部单元基板的顶表面上，并且通过在孔76内延伸的连接与上部单元基板的导电特征电连接。

公开(公告)号：WO2008036208A2

公开(公告)日：2008-03-27

申请号：PCT/US2007/020038

申请日：2007-09-14

Applicant: TESSERA, INC. ,  KANG, Teck-Gyu ,  HABA, Belgacem ,  GAO, Guilian

Inventor： KANG, Teck-Gyu ,  HABA, Belgacem ,  GAO, Guilian

IPC: H01L21/60 ,  H01L23/485

CPC classification number: H01L24/16 ,  H01L21/4853 ,  H01L23/3114 ,  H01L23/49811 ,  H01L24/02 ,  H01L24/11 ,  H01L24/12 ,  H01L24/81 ,  H01L2224/02125 ,  H01L2224/0231 ,  H01L2224/0236 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/11334 ,  H01L2224/13023 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/81801 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/19042 ,  H01L2224/29099

Abstract: Wafer level chip packages including risers (230) having sloped sidewalls (206) and methods of fabricating such chip packages are disclosed. The inventive wafer level chip packages may advantageously be used in various microelectronic assemblies.

Abstract translation: 公开了包括具有倾斜侧壁（206）的立管（230）和制造这种芯片封装的方法的晶片级芯片封装。 本发明的晶片级芯片封装可有利地用于各种微电子组件中。

公开(公告)号：WO2007059193A2

公开(公告)日：2007-05-24

申请号：PCT/US2006044301

申请日：2006-11-14

Applicant: TESSERA INC ,  HUMPSTON GILES ,  NYSTROM MICHAEL J

Inventor： HUMPSTON GILES ,  NYSTROM MICHAEL J

IPC: H01L21/00

CPC classification number: H01L27/14618 ,  H01L2224/48091 ,  H01L2224/48464 ,  H01L2924/00014

Abstract: A microelectronic element such as an imaging semiconductor chip (72) is packaged by bonding a lid wafer (20') having recesses (32) open to its bottom surface to a device wafer (50) including a plurality of the microelectronic elements or chips, so that the recesses overlie active regions such as imaging regions (58) of the device wafer. Where the devices include microlenses (60) associated with an imaging region of each chip, the microlenses may be received in the recesses. Land regions (24') of the lid wafer may be disposed very close to the top surface (52) of the device wafer, as for example, abutting the top surface of the device wafer or separated from such top surface only by an extremely thin coating of a bonding material such as an adhesive or solder. The bonded lid wafer and device wafer may be severed to form individual units (70) . The top surface (22) of the lid wafer may be precisely parallel with the top surface of the device wafer.

Abstract translation: 诸如成像半导体芯片（72）的微电子元件通过将具有其底表面开口的凹口（32）的盖晶片（20'）结合到包括多个微电子元件或芯片的器件晶片（50）而被封装， 使得凹槽覆盖诸如器件晶片的成像区域（58）的有源区域。 在装置包括与每个芯片的成像区域相关联的微透镜（60）的情况下，微透镜可以被容纳在凹部中。 盖晶片的区域（24'）可以非常靠近器件晶片的顶表面（52）设置，例如，邻接器件晶片的顶表面或与顶表面分离，仅极薄 粘合材料如粘合剂或焊料的涂覆。 接合的盖子晶片和器件晶片可以被切断以形成单独的单元（70）。 盖晶片的顶表面（22）可以精确地平行于器件晶片的顶表面。

公开(公告)号：WO2007021553A3

公开(公告)日：2007-02-22

申请号：PCT/US2006/030121

申请日：2006-08-02

Applicant: TESSERA, INC. ,  TUCKERMAN, David, B. ,  HONER, Kenneth, Allen ,  MCWILLIAMS, Bruce, M. ,  COLELLA, Nicholas, J. ,  GOUDGE, Charles, Lian

Inventor： TUCKERMAN, David, B. ,  HONER, Kenneth, Allen ,  MCWILLIAMS, Bruce, M. ,  COLELLA, Nicholas, J. ,  GOUDGE, Charles, Lian

IPC: H01L27/146

Abstract: Image sensors (10) are provided having a plurality of photodetectors (22) in a detector layer (20). Optionally, an optically transparent substrate (11) is provided for a rear- illuminated sensor architecture. The photodetectors (22) may be arranged in three or more arrays. Typically, each array is contiguous and is associated with light of a different color and/or wavelength. In addition, the arrays may be coplanar, or, in the alternative, located at increasing distances from a light -receiving surface (12) in an at least partially nonoverlapping manner. Also provided are image sensor packages.

公开(公告)号：WO2006091793A1

公开(公告)日：2006-08-31

申请号：PCT/US2006/006554

申请日：2006-02-23

Applicant: TESSERA, INC. ,  HABA, Belgacem

Inventor： HABA, Belgacem

IPC: H01L23/485 ,  H01L21/60

CPC classification number: H01L24/16 ,  G01R31/2896 ,  H01L23/3114 ,  H01L23/3171 ,  H01L23/525 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/81 ,  H01L2224/0231 ,  H01L2224/0233 ,  H01L2224/0236 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/0554 ,  H01L2224/1132 ,  H01L2224/1147 ,  H01L2224/13016 ,  H01L2224/13023 ,  H01L2224/13099 ,  H01L2224/13147 ,  H01L2224/16 ,  H01L2224/81801 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01074 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2224/29099

Abstract: A microelectronic assembly includes a microelectronic element (20), such as a semiconductor wafer or semiconductor chip, having a first surface (22) and contacts (24) accessible at the first surface (22), and a compliant layer (26) overlying the first surface of the microelectronic element, the compliant layer (26) having openings in substantial alignment with the contacts (24) of the microelectronic element. The assembly desirably includes conductive posts (38) overlying the compliant layer (26) and projecting away from the first surface (22) of the microelectronic element (20), the conductive posts (38) being electrically interconnected with the contacts (24) of the microelectronic element (20) by elongated, electrically conductive elements extending between the contacts (24) and the conductive posts (38).

Abstract translation: 微电子组件包括具有在第一表面（22）可接近的第一表面（22）和触点（24）的微电子元件（20），例如半导体晶片或半导体芯片，以及柔性层（26），其覆盖 微电子元件的第一表面，顺应层（26）具有与微电子元件的触点（24）基本对准的开口。 组件理想地包括覆盖顺应层（26）并远离微电子元件（20）的第一表面（22）突出的导电柱（38），导电柱（38）与触点（24）电互连 所述微电子元件（20）由在所述触头（24）和所述导电柱（38）之间延伸的细长的导电元件。

公开(公告)号：WO2005065424A3

公开(公告)日：2006-07-20

申请号：PCT/US2004044088

申请日：2004-12-21

Applicant: TESSERA INC ,  HABA BELGACEM ,  BEROZ MASUD ,  HUMPSTON GILES ,  PARK JAE M

Inventor： HABA BELGACEM ,  BEROZ MASUD ,  HUMPSTON GILES ,  PARK JAE M

IPC: H01R13/62 ,  H01L21/48 ,  H01L23/13 ,  H01R13/24

CPC classification number: H01L23/13 ,  H01L21/4846 ,  H01L2924/0002 ,  H01R13/2414 ,  H01R13/2464 ,  H01L2924/00

Abstract: A microelectronic package includes a mounting structure (136), a microelectronic element associated with the mounting structure, and a plurality of conductive posts (146) physically connected to the mounting structure and electrically connected to the microelectronic element. The conductive posts (146) project from the mounting structure (136) in an upward direction (Z), at least one of the conductive posts being an offset post. Each offset post has a base (154) connected to the mounting structure (136), the base of each offset post defining a centroid (156). Each offset post also defines an upper extremity (178) having a centroid (160), the centroid of the upper extremity being offset from the centroid (156) of the base (154) in a horizontal offset direction transverse to the upward direction (Z). The mounting structure (136) is adapted to permit tilting of each offset post about a horizontal axis so that the upper extremities (178) may wipe across a contact pad of an opposing circuit board.

Abstract translation: 微电子封装包括安装结构（136），与安装结构相关联的微电子元件以及物理连接到安装结构并电连接到微电子元件的多个导电柱（146）。 导电柱（146）从安装结构（136）沿向上的方向（Z）突出，至少一个导电柱是偏移柱。 每个偏移柱具有连接到安装结构（136）的基部（154），每个偏移柱的基部限定重心（156）。 每个偏移柱还限定具有质心（160）的上端（178），上端的质心在垂直于向上方向（Z）的水平偏移方向上偏离基座（154）的重心（156） ）。 安装结构（136）适于允许每个偏移柱绕水平轴线倾斜，使得上端（178）可以擦拭相对电路板的接触垫。

公开(公告)号：WO2006071611A1

公开(公告)日：2006-07-06

申请号：PCT/US2005/046012

申请日：2005-12-19

Applicant: TESSERA, INC. ,  CRISP, Richard D. ,  HARA, Belgacem ,  HUMPSTON, Giles

Inventor： CRISP, Richard D. ,  HARA, Belgacem ,  HUMPSTON, Giles

IPC: H01L25/065

CPC classification number: H01L24/73 ,  H01L25/0657 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16145 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/48465 ,  H01L2224/73207 ,  H01L2224/73257 ,  H01L2225/06572 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/07811 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A microelectronic assembly includes a first microelectronic element (110, 125) having conductive posts (130) extending from one major surface, and a second microelectronic element (140) which is electrically interconnected with the first microelectronic element by the conductive posts. The interconnected elements may have coordinated functionality, such as where one microelectronic element is a field programmable gate array and the other microelectronic element is a memory device. In a manufacturing process, a transfer substrate (215) is used to transfer solder masses (210') onto the conductive posts or onto contacts on the second microelectronic element. The solder masses are then used to electrically interconnect the conductive posts with the contacts.

Abstract translation: 微电子组件包括具有从一个主表面延伸的导电柱（130）的第一微电子元件（110,125）和通过导电柱与第一微电子元件电互连的第二微电子元件（140）。 互连的元件可以具有协调的功能，例如其中一个微电子元件是现场可编程门阵列，而另一微电子元件是存储器件。 在制造过程中，转移衬底（215）用于将焊料块（210'）转移到导电柱上或第二微电子元件上的触点上。 焊料块然后用于将导电柱与触点电互连。

公开(公告)号：WO2006044219A3

公开(公告)日：2006-04-27

申请号：PCT/US2005/035962

申请日：2005-10-06

Applicant: TESSERA, INC. ,  HUMPSTON, Giles ,  MCWILIAMS, Bruce, M

Inventor： HUMPSTON, Giles ,  MCWILIAMS, Bruce, M

IPC: H01L21/50 ,  B81B7/00 ,  G01N21/59

Abstract: A microelectronic package may include front and rear covers (46', 60') overlying the front and rear surfaces of a microelectronic element (22') such as an infrared sensor and spaces between the microelectronic element and the covers to provide thermal isolation. A sensing unit including a microelectronic package may include a reflector (76) spaced from the front cover to provide an analyte space, and the microelectronic element may include an emitter (28) and a detector (30) so that radiation directed from the emitter will be reflected by the sensor to the detector, and such radiation will be affected by the properties of the analyte in the analyte space. Such a unit provides a compact, economical chemical sensor. Other packages include elements such as valves (515, 521) for passing fluids into and out of the spaces within the package itself.