公开(公告)号：WO2011013091A2

公开(公告)日：2011-02-03

申请号：PCT/IB2010/053457

申请日：2010-07-29

Applicant: GLOBALFOUNDRIES INC. ,  WALTER, Axel ,  LEHR, Matthias

Inventor： WALTER, Axel ,  LEHR, Matthias

CPC classification number: H01L23/481 ,  H01L23/3114 ,  H01L23/3192 ,  H01L23/3677 ,  H01L23/5283 ,  H01L23/53238 ,  H01L23/552 ,  H01L23/562 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/12 ,  H01L24/13 ,  H01L2224/03 ,  H01L2224/0401 ,  H01L2224/05018 ,  H01L2224/05022 ,  H01L2224/05147 ,  H01L2224/05541 ,  H01L2224/05548 ,  H01L2224/05554 ,  H01L2224/05558 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/0558 ,  H01L2224/05639 ,  H01L2224/05647 ,  H01L2224/06133 ,  H01L2224/1148 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/81191 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/10253 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01L2924/351 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A bump structure or pillar structure formed above a metallization system of a complex semiconductor device may include a stress buffer layer (260), which may efficiently distribute the resulting mechanical stress which may typically occur during the chip package interaction due to a thermal mismatch of these components. The stress buffer layer (260) comprises copper-based buffer regions (265) that cover a significant portion of the overall surface, wherein a thickness of approximately 3- 10 μm may also be used. Moreover, the buffer regions (265) may efficiently replace aluminum as a terminal metal active region.

Abstract translation: 形成在复合半导体器件的金属化系统之上的凸起结构或柱结构可以包括应力缓冲层（260），其可以有效地分布由于这些的热失配而在芯片封装相互作用期间通常发生的所得到的机械应力 组件。 应力缓冲层（260）包括覆盖整个表面的重要部分的铜基缓冲区（265），其中也可以使用约3-10μm的厚度。 此外，缓冲区（265）可以有效地代替铝作为末端金属活性区。

公开(公告)号：WO2010049087A3

公开(公告)日：2010-06-24

申请号：PCT/EP2009007549

申请日：2009-10-21

Applicant: ADVANCED MICRO DEVICES INC ,  PLATZ ALEXANDER ,  KUECHENMEISTER FRANK ,  LEHR MATTHIAS

Inventor： PLATZ ALEXANDER ,  KUECHENMEISTER FRANK ,  LEHR MATTHIAS

IPC: H01L23/485 ,  H01L21/60 ,  H01L23/31

CPC classification number: H01L24/12 ,  H01L23/3171 ,  H01L23/3192 ,  H01L23/562 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/0401 ,  H01L2224/05027 ,  H01L2224/05093 ,  H01L2224/05096 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/10126 ,  H01L2224/1147 ,  H01L2224/11472 ,  H01L2224/11902 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/351 ,  H01L2224/13099 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/05552

Abstract: In a metallization system of a sophisticated semiconductor device, metal pillars 271 may be provided so as to exhibit an increased efficiency in distributing any mechanical stress exerted thereon. This may be accomplished by significantly increasing the surface area of the final passivation layer 260 that is in tight mechanical contact with the metal pillar, for example by providing an additional stress distribution element 272 in contact with the pillar 271 and the final passivation layer 260.

Abstract translation: 在复杂的半导体器件的金属化系统中，可以提供金属柱271，以便分布施加在其上的任何机械应力的分布效率提高。 这可以通过显着增加与金属柱紧密机械接触的最终钝化层260的表面积，例如通过提供与柱271和最终钝化层260接触的附加应力分布元件272来实现。

公开(公告)号：WO2010022970A1

公开(公告)日：2010-03-04

申请号：PCT/EP2009/006258

申请日：2009-08-28

Applicant: ADVANCED MICRO DEVICES, INC. ,  GRILLBERGER, Michael ,  LEHR, Matthias, Uwe

Inventor： GRILLBERGER, Michael ,  LEHR, Matthias, Uwe

IPC: H01L23/58 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L23/522 ,  H01L23/53295 ,  H01L23/562 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/051 ,  H01L2224/05572 ,  H01L2224/056 ,  H01L2224/13 ,  H01L2224/16 ,  H01L2924/1433 ,  H01L2924/00014

Abstract: By dividing a single chip area into individual sub areas (200a, 200b, 200c on the basis of one or more stress relaxation regions 280a, 280b,) a thermally- induced stress in each of the sub areas may be reduced during operation of complex integrated circuits, thereby enhancing the overall reliability of complex metallization systems comprising low-k dielectric materials or ULK material. Consequently, a high number of stacked metallization layers in combination with increased lateral dimensions of the semiconductor chip (200) may be used compared to conventional strategies.

Abstract translation: 通过将单个芯片区域划分成各个子区域（200a，200b，200c，基于一个或多个应力松弛区域280a，280b），每个子区域中的热诱导应力可以在复合集成 电路，从而提高包括低k电介质材料或ULK材料的复杂金属化系统的整体可靠性。 因此，与常规策略相比，可以使用大量堆叠的金属化层与半导体芯片（200）的增加的横向尺寸的组合。

公开(公告)号：WO2009040314A2

公开(公告)日：2009-04-02

申请号：PCT/EP2008/062552

申请日：2008-09-19

Applicant: WESTFÄLISCHE WILHELMS UNIVERSITÄT MÜNSTER ,  LEHR, Matthias ,  BOVENS, Stefanie

Inventor： LEHR, Matthias ,  BOVENS, Stefanie

IPC: C07D209/42 ,  C07D413/04 ,  A61K31/40 ,  A61K31/404 ,  A61K31/415 ,  A61P7/02 ,  A61P17/00 ,  A61P29/00

CPC classification number: C07D209/42 ,  C07D413/04

Abstract: Die vorliegende Erfindung betrifft neue heteroarylsubstituierte Acetonderivate, die das Enzym Phospholipase A 2 hemmen, sowie pharmazeutische Mittel umfassend diese Verbindungen.

Abstract translation: 本发明涉及抑制酶磷脂酶A2的新的杂芳基丙酮衍生物，以及包含这些化合物的药物组合物。

公开(公告)号：WO2008054680A3

公开(公告)日：2008-05-08

申请号：PCT/US2007/022683

申请日：2007-10-26

Applicant: ADVANCED MICRO DEVICES, INC. ,  LEHR, Matthias ,  KUECHENMEISTER, Frank ,  LEHMANN, Lothar ,  WIELAND, Marcel ,  PLATZ, Alexander ,  WALTER, Axel ,  JUNGNICKEL, Gotthard

Inventor： LEHR, Matthias ,  KUECHENMEISTER, Frank ,  LEHMANN, Lothar ,  WIELAND, Marcel ,  PLATZ, Alexander ,  WALTER, Axel ,  JUNGNICKEL, Gotthard

IPC: H01L23/485 ,  H01L21/60

Abstract: By directly forming an underbump metallization layer (211) on a contact region (202A) of the last metallization layer, the formation of any other terminal metals, such as aluminum and corresponding adhesion/barrier layers, may be avoided. Consequently, the thermal and electrical behavior of the resulting bump structure (212) may be improved, while process complexity may be significantly reduced.

公开(公告)号：WO2007040860A1

公开(公告)日：2007-04-12

申请号：PCT/US2006/032919

申请日：2006-08-23

Applicant: ADVANCED MICRO DEVICES, INC. ,  LEHR, Matthias ,  KOSCHINSKY, Frank ,  NOPPER, Markus

Inventor： LEHR, Matthias ,  KOSCHINSKY, Frank ,  NOPPER, Markus

IPC: H01L21/768 ,  H01L21/288

CPC classification number: H01L23/53238 ,  H01L21/288 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76849 ,  H01L21/76865 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: By providing a conductive capping layer (106) for metal-based interconnect lines, an enhanced performance with respect to electromigration may be achieved. Moreover, a corresponding manufacturing technique is provided in which via openings (110) may be reliably etched into the capping layer (106) without exposing the underlying metal (105b), such as copper-based material, thereby also providing enhanced electromigration performance, especially at the transitions between copper lines and vias.

Abstract translation: 通过为基于金属的互连线提供导电覆盖层（106），可以实现相对于电迁移的增强的性能。 此外，提供了相应的制造技术，其中可以将通孔（110）可靠地蚀刻到覆盖层（106）中而不暴露诸如铜基材料的下面的金属（105b），从而也提供增强的电迁移性能，特别是 在铜线和通孔之间的过渡。

公开(公告)号：WO2010024932A3

公开(公告)日：2010-08-12

申请号：PCT/US2009004916

申请日：2009-08-29

Applicant: GLOBALFOUNDRIES INC ,  MEYER ANDREAS ,  LEHR MATTHIAS ,  KUECHENMEISTER FRANK

Inventor： MEYER ANDREAS ,  LEHR MATTHIAS ,  KUECHENMEISTER FRANK

IPC: H01L23/24 ,  H01L21/56 ,  H01L21/60 ,  H01L23/31 ,  H01L23/485

CPC classification number: H01L24/85 ,  H01L21/56 ,  H01L23/24 ,  H01L23/3121 ,  H01L23/3171 ,  H01L24/02 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/04042 ,  H01L2224/05009 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05647 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48247 ,  H01L2224/48453 ,  H01L2224/48463 ,  H01L2224/48507 ,  H01L2224/48624 ,  H01L2224/48639 ,  H01L2224/48647 ,  H01L2224/48724 ,  H01L2224/48739 ,  H01L2224/48747 ,  H01L2224/48824 ,  H01L2224/48839 ,  H01L2224/48847 ,  H01L2224/85201 ,  H01L2224/85205 ,  H01L2224/85375 ,  H01L2224/8592 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/01073 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/16152 ,  H01L2924/16195 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/351 ,  H01L2224/78 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2924/00012

Abstract: The wire bond structure of sophisticated metallization systems, for instance based on copper, may be provided without a terminal aluminum layer and without any passivation layers for exposed copper surfaces (212S) by providing a fill material (250) after the wire bonding process in order to encapsulate at least the sensitive metal surfaces (212S) and a portion of the bond wire (230). Hence, significant cost reduction, reduced cycle times and a reduction of the required process steps may be accomplished independently from the wire bond materials used. Thus, integrated circuits requiring a sophisticated metallization system may be connected by wire bonding to the corresponding package (260) or carrier substrate with a required degree of reliability based on a corresponding fill material (250) for encapsulating at least the sensitive metal surfaces (212S).

Abstract translation: 通过在引线接合工艺之后提供填充材料（250），可以提供例如基于铜的精密金属化系统的引线接合结构，而无需端子铝层并且没有用于暴露的铜表面（212S）的任何钝化层 以封装至少敏感金属表面（212S）和一部分键合线（230）。 因此，显着的成本降低，减少的循环时间和所需的工艺步骤的减少可独立于所使用的丝焊材料来实现。 因此，基于用于封装至少敏感金属表面（212S）的相应填充材料（250），需要精密金属化系统的集成电路可以通过引线接合与具有所需可靠程度的可靠程度的相应封装（260） ）。

公开(公告)号：WO2009073087A2

公开(公告)日：2009-06-11

申请号：PCT/US2008/012989

申请日：2008-11-21

Applicant: ADVANCED MICRO DEVICES, INC. ,  LEHR, Matthias ,  KUECHENMEISTER, Frank ,  THIERBACH, Steffi

Inventor： LEHR, Matthias ,  KUECHENMEISTER, Frank ,  THIERBACH, Steffi

IPC: H01L21/60 ,  H01L23/485 ,  H01L23/544

CPC classification number: H01L24/11 ,  H01L22/34 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05073 ,  H01L2224/05644 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13155 ,  H01L2224/13184 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01068 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00

Abstract: In sophisticated semiconductor devices (200) including copper-based metallization systems, a substantially aluminum-free bump structure (212D) in device regions (250D) and a substantially aluminum-free wire bond structure (212T) in test regions (250T) may be formed on the basis of a manufacturing process resulting in identical final dielectric layer stacks (203) in these device areas. The number of process steps may be reduced by making a decision as to whether a substrate is to become a product substrate or test substrate for estimating the reliability of actual semiconductor devices (202D). For example, nickel contact elements may be formed above copper-based contact areas wherein the nickel may provide a base for wire bonding or forming a bump material thereon.

Abstract translation: 在包括铜基金属化系统的复杂半导体器件（200）中，在测试区域（250T）中的器件区域（250D）中的基本上不含铝的凸块结构（212D）和基本上不含铝的引线键合结构（212T）可以是 在制造工艺的基础上形成，从而在这些器件区域中产生相同的最终电介质层叠层（203）。 可以通过判断衬底是否成为用于估计实际半导体器件（202D）的可靠性的产品衬底或测试衬底来降低工艺步骤的数量。 例如，镍接触元件可以形成在铜基接触区域之上，其中镍可以提供用于引线接合的基底或在其上形成凸块材料。

公开(公告)号：WO2007005136A1

公开(公告)日：2007-01-11

申请号：PCT/US2006/019720

申请日：2006-05-23

Applicant: ADVANCED MICRO DEVICES, INC. ,  LEHR, Matthias ,  FROHBERG, Kai ,  SCHWAN, Christoph

Inventor： LEHR, Matthias ,  FROHBERG, Kai ,  SCHWAN, Christoph

IPC: H01L21/8238

CPC classification number: H01L29/7843 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823835 ,  H01L21/823864

Abstract: A technique is provided that enables the formation of metal suicide individually for N-channel transistors and P-channel transistors, while at the same time a strain-inducing mechanism is also provided individually for each transistor type. In this way, a cobalt suicide (130, 230) having a reduced distance to the channel region of an NMOS transistor (120, 220) may be provided, while a P-channel transistor (140, 240) may receive a highly conductive nickel suicide (150, 250), without unduly affecting or compromising the characteristics of the N-channel transistor (120, 220).

Abstract translation: 提供了一种技术，其能够分别形成用于N沟道晶体管和P沟道晶体管的金属硅化物，同时针对每个晶体管类型单独提供应变诱发机制。 以这种方式，可以提供具有与NMOS晶体管（120,220）的沟道区域的距离减小的钴硅化物（130,230），而P沟道晶体管（140,240）可以接收高导电性镍 自杀（150,250），而不会不适当地影响或损害N沟道晶体管（120,220）的特性。

公开(公告)号：WO2011013091A3

公开(公告)日：2011-11-03

申请号：PCT/IB2010053457

申请日：2010-07-29

Applicant: GLOBALFOUNDRIES INC ,  WALTER AXEL ,  LEHR MATTHIAS

Inventor： WALTER AXEL ,  LEHR MATTHIAS

IPC: H01L23/485 ,  H01L21/60

CPC classification number: H01L23/481 ,  H01L23/3114 ,  H01L23/3192 ,  H01L23/3677 ,  H01L23/5283 ,  H01L23/53238 ,  H01L23/552 ,  H01L23/562 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/12 ,  H01L24/13 ,  H01L2224/03 ,  H01L2224/0401 ,  H01L2224/05018 ,  H01L2224/05022 ,  H01L2224/05147 ,  H01L2224/05541 ,  H01L2224/05548 ,  H01L2224/05554 ,  H01L2224/05558 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/0558 ,  H01L2224/05639 ,  H01L2224/05647 ,  H01L2224/06133 ,  H01L2224/1148 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/81191 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/10253 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A bump structure or pillar structure formed above a metallization system of a complex semiconductor device may include a stress buffer layer (260), which may efficiently distribute the resulting mechanical stress which may typically occur during the chip package interaction due to a thermal mismatch of these components. The stress buffer layer (260) comprises copper-based buffer regions (265) that cover a significant portion of the overall surface, wherein a thickness of approximately 3- 10 µm may also be used. Moreover, the buffer regions (265) may efficiently replace aluminum as a terminal metal active region.

Abstract translation: 形成在复杂半导体器件的金属化系统上方的凸块结构或柱结构可以包括应力缓冲层（260），该应力缓冲层可以有效地分布由于这些芯片封装相互作用期间的热失配而可能通常发生的机械应力 组件。 应力缓冲层（260）包括覆盖整个表面的显着部分的铜基缓冲区（265），其中也可以使用大约3至10μm的厚度。 而且，缓冲区（265）可以有效地替代铝作为端金属活性区域。