公开(公告)号：WO2004107440B1

公开(公告)日：2005-07-07

申请号：PCT/JP2004007377

申请日：2004-05-28

Applicant: SHARP KK ,  TOSHIBA CORP ,  RENESAS TECH CORP ,  SATOH TOMOTOSHI ,  NEMOTO YOSHIHIKO ,  TAKAHASHI KENJI ,  AKIYAMA YUKIHARU

Inventor： SATOH TOMOTOSHI ,  NEMOTO YOSHIHIKO ,  TAKAHASHI KENJI ,  AKIYAMA YUKIHARU

IPC: H01L25/18 ,  H01L23/48 ,  H01L25/065 ,  H01L25/10 ,  H01L25/11 ,  H01L29/06 ,  H01L25/07

CPC classification number: H01L24/06 ,  H01L23/481 ,  H01L25/0657 ,  H01L29/0657 ,  H01L2224/0401 ,  H01L2224/05554 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2225/06593 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01055 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10155 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/3011

Abstract: It is possible to provide electronic parts for assembling a module by superimposing a plurality of layers with identical configuration. Each terminal of each terminal groups (31 to 36) is formed to be rotationally symmetric with a predetermined number of settings or symmetric with respect to the plane containing the rotational symmetry and the symmetric axis line. Each of the terminals (A0 to A7, RFCG) of common connection terminal groups (32, 36)has a connection portion formed on the surface section of both sides of the superimposing direction. Among the terminals of individual connection terminal groups (31, 33), a particular terminal CS;KEY has a connection portion formed at least on one of the sides of the superimposing direction of the surface section while the remaining associated terminal NC;DMY has a connection portion formed on the surface section of both sides of the superimposing direction. Such an electronic part (20) can be shifted by the angle obtained by dividing 360 degrees by the predetermined number of settings or added and reversed so as to be superimposed, thereby preferably assembling a module.

Abstract translation: 可以通过叠加具有相同结构的多个层来提供用于组装模块的电子部件。 每个端子组（31至36）的每个端子被形成为以预定数量的设置旋转对称，或者相对于包含旋转对称性和对称轴线的平面对称。 公共连接端子组（32,36）的端子（A0〜A7，RFCG）中的每一个具有形成在叠加方向两侧的表面部分上的连接部。 在单个连接端子组（31,33）的端子中，特定端子CS; KEY具有形成在表面部分的重叠方向的至少一个侧面上的连接部分，而剩余的相关端子NC; DMY具有 连接部分形成在叠加方向的两侧的表面部分上。 这样的电子部件（20）可以通过将360度除以预定数量的设置而获得的角度被移位，或者相加或相加以被叠加，从而优选地组装模块。

公开(公告)号：WO2004036463A9

公开(公告)日：2005-01-20

申请号：PCT/JP0312839

申请日：2003-10-07

Applicant: RENESAS TECH CORP ,  TANIMOTO TADAAKI ,  KAMADA MASURAO

Inventor： TANIMOTO TADAAKI ,  KAMADA MASURAO

IPC: G06F17/50

CPC classification number: G06F17/5045

Abstract: A compiler is supplied with a pseudo C description (1) which can describe parallel operation at the statement level by a clock boundary and a register assignment statement with a cycle accuracy, identifies the register assignment statement (S2), generates an executable C description (3), extracts a state machine in which the number of states has been reduced, and judges whether any loop executed by 0 cycle is present (S5). If none, the compiler generates a circuit description (4) capable of synthesizing a logic. Thus, a pseudo C description having C description in which a clock boundary is explicitly inserted is input. Since the pseudo C description capable of parallel description at the statement level by the register assignment statement is input, it is possible to express the pipeline operation accompanied by stall operation.

Abstract translation: 一个编译器提供了一个伪C描述（1），它可以通过一个时钟边界和一个具有周期精度的寄存器分配语句来描述语句级的并行操作，识别寄存器分配语句（S2），生成一个可执行的C描述（ 3），提取状态数已经减少的状态机，并判断是否存在0循环执行的循环（S5）。 如果没有，则编译器产生能够合成逻辑的电路描述（4）。 因此，输入具有明确插入时钟边界的C描述的伪C描述。 由于能够通过寄存器分配语句在语句级并行描述的伪C描述被输入，所以可以表示伴随失速操作的管道操作。

公开(公告)号：WO2008002813A3

公开(公告)日：2009-01-08

申请号：PCT/US2007071710

申请日：2007-06-20

Applicant: GRANDIS INC ,  RENESAS TECH CORP ,  CHEN EUGENE YOUJUN ,  HUAI YIMING ,  PANCHULA ALEX FISCHER ,  WANG LIEN-CHANG ,  LUO XIAO

Inventor： CHEN EUGENE YOUJUN ,  HUAI YIMING ,  PANCHULA ALEX FISCHER ,  WANG LIEN-CHANG ,  LUO XIAO

IPC: G11C11/15

CPC classification number: G11C11/16

Abstract: A method and system for providing a magnetic memory is described. The magnetic memory includes magnetic storage cells in an array, bit lines, and source lines. Each magnetic storage cell includes at least one magnetic element. The magnetic element(s) are programmable by write currents driven through the magnetic element(s). Each magnetic element has free and pinned layer(s) and a dominant spacer. The magnetic memory is configured such that either the read current(s) flow from the free layer(s) to the dominant spacer if the maximum low resistance state read current divided by the minimum low resistance state write current is greater than the maximum high resistance state read current divided by the minimum high resistance state write current or the read current(s) flow from the dominant spacer to the free layer(s) if the maximum low resistance state read current divided by the minimum low resistance state write current is less than the maximum high resistance state read current divided by the minimum high resistance state write current.

Abstract translation: 描述了一种用于提供磁存储器的方法和系统。 磁存储器包括阵列中的磁存储单元，位线和源极线。 每个磁存储单元包括至少一个磁性元件。 磁性元件可以通过驱动通过磁性元件的写入电流来编程。 每个磁性元件具有自由和固定的层和主要间隔物。 如果最大低电阻状态读取电流除以最小低电阻状态写入电流除以最大高电阻，则磁存储器被配置为使得读取电流从自由层流向主要间隔物 如果最小低电阻状态读取电流除以最小低电阻状态写入电流，则状态读取电流除以最小高电阻状态写入电流或从主要间隔物到自由层的读取电流（s） 比最大高电阻状态读取电流除以最小高电阻状态写入电流。

公开(公告)号：WO2008045684A3

公开(公告)日：2008-07-24

申请号：PCT/US2007079584

申请日：2007-09-26

Applicant: RENESAS TECH CORP ,  KUIVENHOVEN ROBERT

Inventor： KUIVENHOVEN ROBERT

IPC: B60R21/16

CPC classification number: B60R21/0173

Abstract: A squib driver module comprises a squib circuit for deploying a squib, e.g., in an airbag assembly, the squib circuit including a high side driver and a low side driver in combination for driving a firing signal to the squib: a circuit for activating the firing signal in response to a firing condition; squib diagnostic circuits for conducting diagnostic tests without activating the firing signal and without delivering a diagnostic signal equivalent of the firing signal to the squib, and for generating digital fault information based on the tests; registers for storing the fault information; logic for recognizing a fault condition based on the fault information; and a communication module for communicating the fault condition to a microprocessor unit. The squib diagnostic circuit may include node voltage diagnostic circuits, USD and/or LSD open/short circuits, USD and/or LSD driver fault diagnostic circuits, squib-squib short diagnostic circuits, and/or squib resistance diagnostic circuits.

Abstract translation: 爆管驱动器模块包括用于在例如安全气囊组件中部署爆管的爆管电路，包括高侧驱动器和低侧驱动器的爆管电路组合用于将点火信号驱动到爆管：用于激活点火的电路 响应于点火状态的信号; 点火诊断电路，用于进行诊断测试而不激活点火信号，并且不向爆管发送等效于点火信号的诊断信号，并且用于基于测试产生数字故障信息; 用于存储故障信息的寄存器; 基于故障信息识别故障状态的逻辑; 以及用于将故障状况传送到微处理器单元的通信模块。 爆管诊断电路可以包括节点电压诊断电路，美元和/或LSD开路/短路，美元和/或LSD驱动器故障诊断电路，爆管短路诊断电路和/或爆管电阻诊断电路。

公开(公告)号：WO2007043136A9

公开(公告)日：2007-06-14

申请号：PCT/JP2005018350

申请日：2005-10-04

Applicant: RENESAS TECH CORP ,  YOSHIDA SHOJI ,  WATANABE KOZO

Inventor： YOSHIDA SHOJI ,  WATANABE KOZO

IPC: G11C16/02 ,  G11C16/04

CPC classification number: G11C16/0483 ,  G11C16/10

Abstract: A NAND-type flash memory includes a memory array (2) having a plurality of nonvolatile memory transistor (QM) and a control circuit (8). The nonvolatile memory transistor has a tunnel insulation film (15), an insulating charge accumulation film (16), and a memory gate (18) on a substrate region (11) and stores information by a difference in a threshold value viewed from the memory gate. The threshold value voltage is a negative voltage. The memory array has a plurality of series circuits (STRG) consisting of a plurality of nonvolatile memory transistors connected in series and word lines (WL0 to WLn) connected to respective row of the memory gates of the nonvolatile memory transistors constituting the series circuit. When information stored in the nonvolatile memory transistor is read out, the control circuit makes the word line connected to the nonvolatile memory transistor of read selection at a potential identical to the substrate region and makes the word line connected to the nonvolatile memory transistor of read non-selection at a potential identical to the source potential.

Abstract translation: NAND型闪存包括具有多个非易失性存储晶体管（QM）和控制电路（8）的存储器阵列（2）。 非易失性存储器晶体管在衬底区域（11）上具有隧道绝缘膜（15），绝缘电荷积蓄膜（16）和存储器栅极（18），并且通过从存储器观察的阈值差异存储信息 门。 阈值电压是负电压。 存储器阵列具有由串联连接的多个非易失性存储器晶体管和连接到构成串联电路的非易失性存储器晶体管的各个存储器栅极的字线（WL0至WLn）组成的多个串联电路（STRG）。 当读出存储在非易失性存储器晶体管中的信息时，控制电路使与读取选择的非易失性存储器晶体管连接的字线处于与衬底区域相同的电位，并且使字线连接到非读取非易失性存储器晶体管 - 选择与源潜力相同的潜力。

公开(公告)号：WO2006047061A8

公开(公告)日：2006-12-07

申请号：PCT/US2005036059

申请日：2005-10-07

Applicant: SEMEQUIP INC ,  RENESAS TECH CORP ,  JACOBSON DALE C ,  KAWASAKI YOJI

Inventor： JACOBSON DALE C ,  KAWASAKI YOJI

IPC: H01L21/336 ,  H01L21/425

CPC classification number: H01L21/26513 ,  H01L21/26586 ,  H01L21/324 ,  H01L21/823814 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/6659

Abstract: A method of producing ultra shallow junctions (104) for PMOS transistors, which eliminates the need for pre-amorphization implants, is disclosed. The method utilizes octadecaborane, B 18 H 22 . In accordance with the present invention, the pre-­amorphizing step may be eliminated, greatly reducing cost per processed wafer. An appropriate process sequence has been suggested to take advantage of cluster ion implantation for PMOS manufacturing. In addition, the novel use of tilted implants for the source/drain extension and for pocket implants has been described.

Abstract translation: 公开了一种产生用于PMOS晶体管的超浅结（104）的方法，其消除了对非晶化前注入的需要。 该方法利用十八硼烷B 18 SUB 22 22。 根据本发明，可以消除预非晶化步骤，大大降低每个加工晶片的成本。 已经提出了适当的工艺顺序以利用用于PMOS制造的簇离子注入。 另外，已经描述了倾斜植入物用于源极/漏极延伸部分和口袋植入物的新颖用途。

公开(公告)号：WO2005072065A3

公开(公告)日：2005-10-06

申请号：PCT/JP2004000955

申请日：2004-01-30

Applicant: RENESAS TECH CORP ,  WATANABE KAZUKI ,  MATSUSHITA KAZUHIRO ,  KUBOTA MASARU

Inventor： WATANABE KAZUKI ,  MATSUSHITA KAZUHIRO ,  KUBOTA MASARU

IPC: G06K19/07 ,  H02J17/00

CPC classification number: G06K19/0723 ,  G06K19/0701

Abstract: A semiconductor integrated circuit device for stable transmission through an antenna, a noncontact type IC card using the semiconductor integrated circuit device, and a portable information terminal. The semiconductor integrated circuit device is provided with antenna terminals LA and LB, a power supply circuit (B5) and an internal circuit (B8). The antenna terminals LA and LB are connected to an antenna (L1). The power supply circuit (B5) is provided with a rectifier/smoothing circuit (B1), which rectifies and smoothes an alternating signal given to an antenna terminal from the antenna to obtain a direct voltage, a shunt regulator (B6), which stabilizes the direct voltage, and a series regulator (B7). The internal circuit (B8) operates by being supplied with a direct current voltage from the power supply circuit. At the time of transmission to a reader/writer, the series regulator operates and the shunt regulator stops, and other than the time of transmission to the reader/writer, the shunt regulator operates and the series regulator stops.

Abstract translation: 一种用于通过天线稳定传输的半导体集成电路器件，使用半导体集成电路器件的非接触型IC卡和便携式信息终端。 半导体集成电路装置具有天线端子LA和LB，电源电路（B5）和内部电路（B8）。 天线端子LA和LB连接到天线（L1）。 电源电路（B5）设置有整流/平滑电路（B1），其对来自天线的天线端子的交替信号进行整流和平滑，以获得直流电压;分流调节器（B6），其使 直流电压和串联调节器（B7）。 内部电路（B8）通过从电源电路提供直流电压来工作。 在传输到读写器时，串联稳压器工作，分流稳压器停止，除了传输到读/写器的时间之外，并联稳压器工作，串联稳压器停止。

公开(公告)号：WO2008010957A2

公开(公告)日：2008-01-24

申请号：PCT/US2007015987

申请日：2007-07-13

Applicant: GRANDIS INC ,  RENESAS TECH CORP ,  YUNFEI DING

Inventor： YUNFEI DING

IPC: G11C11/00

CPC classification number: G11C11/1675 ,  G11C11/161 ,  G11C11/1655 ,  G11C11/1659 ,  G11C11/5607

Abstract: A method and system for providing and utilizing a magnetic memory are described. The magnetic memory includes a plurality of magnetic storage cells. Each magnetic storage cell includes magnetic element(s) programmable due to spin transfer when a write current is passed through the magnetic element(s) and selection device(s). The method and system include driving a first current in proximity to but not through the magnetic element(s) of a portion of the magnetic storage cells. The first current generates a magnetic field. The method and system also include driving a second current through the magnetic element(s) of the portion of the magnetic storage cells. The first and second currents are preferably both driven through bit line(s) coupled with the magnetic element(s). The first and second currents are turned on at a start time. The second current and the magnetic field are sufficient to program the magnetic element(s).

Abstract translation: 描述了一种用于提供和利用磁存储器的方法和系统。 磁存储器包括多个磁存储单元。 每个磁存储单元包括当写入电流通过磁性元件和选择装置时由于自旋转移而可编程的磁性元件。 该方法和系统包括驱动靠近但不通过磁存储单元的一部分的磁性元件的第一电流。 第一电流产生磁场。 该方法和系统还包括驱动第二电流通过磁存储单元的该部分的磁性元件。 第一和第二电流优选地通过与磁性元件耦合的位线驱动。 第一和第二电流在开始时被接通。 第二电流和磁场足以对磁性元件进行编程。

公开(公告)号：WO2005124850A8

公开(公告)日：2007-06-21

申请号：PCT/JP2005010921

申请日：2005-06-15

Applicant: RENESAS TECH CORP ,  IKEDA OSAMU ,  OKAMOTO MASAHIDE ,  HARUTA RYO ,  KAGII HIDEMASA ,  OKA HIROI ,  NAKAMURA HIROYUKI

Inventor： IKEDA OSAMU ,  OKAMOTO MASAHIDE ,  HARUTA RYO ,  KAGII HIDEMASA ,  OKA HIROI ,  NAKAMURA HIROYUKI

IPC: H01L21/52 ,  H01L21/60 ,  H01L23/495

CPC classification number: H01L23/49562 ,  H01L23/49513 ,  H01L23/49524 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/37 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L2224/04026 ,  H01L2224/05111 ,  H01L2224/05139 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05644 ,  H01L2224/2908 ,  H01L2224/29083 ,  H01L2224/29101 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/29118 ,  H01L2224/29123 ,  H01L2224/29124 ,  H01L2224/29139 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/2919 ,  H01L2224/32013 ,  H01L2224/32057 ,  H01L2224/32245 ,  H01L2224/32507 ,  H01L2224/37147 ,  H01L2224/40095 ,  H01L2224/40247 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48644 ,  H01L2224/48699 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83801 ,  H01L2224/83805 ,  H01L2224/84801 ,  H01L2224/85205 ,  H01L2224/92247 ,  H01L2924/00011 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01063 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/15747 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/01032 ,  H01L2924/00012 ,  H01L2924/01022 ,  H01L2924/01026 ,  H01L2924/01083 ,  H01L2924/3512 ,  H01L2224/48744 ,  H01L2924/00015 ,  H01L2224/83205

Abstract: A power semiconductor device having a semiconductor element die-mount-connected onto a lead frame in a leadless manner. Die-mount-connection between a semiconductor element (1) and a lead frame (2) that have large thermal expansion coefficient difference between them, wherein the connection is made by an intermetallic compound layer (200) having a melting point of at least 260æC or by a leadless solder having a melting point of 260æC through 400æC, and thermal stress caused by a temperature cycle is buffered by a metal layer (100) having a melting point of at least 260æC. The leadless die-mount-connection can be made without being melted at reflowing and without causing chip-crack under a thermal stress.

Abstract translation: 一种功率半导体器件，具有半导体元件，其以无引线方式管芯安装到引线框架上。 半导体元件（1）和引线框架（2）之间的模具安装连接，它们之间具有较大的热膨胀系数差，其中，连接是由具有至少260℃的熔点的金属间化合物层（200） 或通过熔点为260℃至400℃的无铅焊料，并且由温度周期引起的热应力由熔点至少为260℃的金属层（100）缓冲。 无引线模具安装连接可以在回流时不熔化而不会在热应力下引起芯片裂纹。

公开(公告)号：WO2007137055A3

公开(公告)日：2008-11-06

申请号：PCT/US2007069014

申请日：2007-05-16

Applicant: GRANDIS INC ,  RENESAS TECH CORP ,  XIAO LUO ,  WANG LIEN-CHANG

Inventor： XIAO LUO ,  WANG LIEN-CHANG

IPC: G11C11/00 ,  G11C11/14 ,  H01L27/088

CPC classification number: H01L27/228 ,  G11C11/16 ,  H01L29/4238

Abstract: A method and system for providing and using a magnetic storage cell and magnetic memory is described. The method and system include providing a magnetic element and providing a selection device. The magnetic element is programmable to a first state by a first write current driven through the magnetic element in a first direction and to a second state by a second write current driven through the magnetic element in a second direction. The selection device is connected with the magnetic element. The selection device includes a gate having an aperture therein. The selection device is configured such that the first write current and second write current are provided to the magnetic element across the aperture.

Abstract translation: 描述了一种用于提供和使用磁存储单元和磁存储器的方法和系统。 该方法和系统包括提供磁性元件并提供选择装置。 磁性元件可通过在第一方向通过磁性元件驱动的第一写入电流而被编程为第一状态，并且通过在第二方向上被驱动通过磁性元件的第二写入电流而被编程为第二状态。 选择装置与磁性元件连接。 选择装置包括其中具有孔的门。 选择装置被配置为使得第一写入电流和第二写入电流被提供给穿过该孔的磁性元件。