公开(公告)号：WO9524730A3

公开(公告)日：1996-02-15

申请号：PCT/US9502678

申请日：1995-03-09

Applicant: PANDA PROJECT

Inventor： CRANE STANFORD W JR ,  PORTUONDO MARIA M

IPC: H05K1/18 ,  H01L23/498 ,  H05K1/11 ,  H05K3/30 ,  H05K3/32 ,  H05K3/34 ,  H05K3/46 ,  H01L

CPC classification number: H01L23/49861 ,  H01L23/49811 ,  H01L2924/0002 ,  H01L2924/181 ,  H05K1/112 ,  H05K3/308 ,  H05K3/321 ,  H05K3/3421 ,  H05K3/4623 ,  H05K2201/09472 ,  H05K2201/09536 ,  H05K2201/09645 ,  H05K2201/10189 ,  H05K2201/1031 ,  H05K2201/10318 ,  H05K2201/10704 ,  H05K2201/10772 ,  H05K2201/10893 ,  Y02P70/611 ,  Y02P70/613 ,  Y10T29/49126 ,  Y10T29/49147 ,  Y10T29/49149 ,  H01L2924/00 ,  H01L2924/00012

Abstract: An apparatus comprising a multi-layer substrate (10) including a plurality of layers of insulative material (12), at least one well (15) formed in at least one of the layers, the well (15) extending from an outer surface of the multi-layer substrate to an inner surface of the multi-layer substrate, and an electrically conductive component (13) formed within the well (15) on the inner surface of the multi-layer substrate; and a device having at least one electrically conductive lead or wire (11) extending into the well (15) and being in direct physical contact with the electrically conductive component (13) formed on the inner surface of the multi-layer substrate. Also, a method of manufacturing an apparatus comprising the steps of forming a multi-layer substrate (10) including a plurality of layers of insulative material (12), at least one well (15) formed in at least one of the layers, the well (15) extending from an outer surface of the multi-layer substrate to an inner surface of the multi-layer substrate, and an electrically conductive component (13) formed within the well (15) on the inner surface of the multi-layer substrate; and extending at least one electrically conductive lead or wire (11) from a device into the well (15) such that the lead or wire is in direct physical contact with the electrically conductive component (13) formed on the inner surface of the multi-layer substrate.

Abstract translation: 半导体管芯封装（30）包括多个导电引线（11）和用于承载电信号的多层结构（10），所述多层结构（10）包括多层绝缘材料（12a-12d ），每个层包括在该层的相对侧上的第一表面和第二表面。 每个引线（11）延伸到完全延伸通过至少一个层的相应的阱（15），并且在一个层的一个表面上底部，阱（15）不通过该表面延伸并电耦合 涉及形成在其对应的井（15）内的导电接合结构（13）。

公开(公告)号：WO1995024730A2

公开(公告)日：1995-09-14

申请号：PCT/US1995002678

申请日：1995-03-09

Applicant: THE PANDA PROJECT

Inventor： THE PANDA PROJECT ,  CRANE, Stanford, W., Jr. ,  PORTUONDO, Maria, M.

IPC: H01L00/00

CPC classification number: H01L23/49861 ,  H01L23/49811 ,  H01L2924/0002 ,  H01L2924/181 ,  H05K1/112 ,  H05K3/308 ,  H05K3/321 ,  H05K3/3421 ,  H05K3/4623 ,  H05K2201/09472 ,  H05K2201/09536 ,  H05K2201/09645 ,  H05K2201/10189 ,  H05K2201/1031 ,  H05K2201/10318 ,  H05K2201/10704 ,  H05K2201/10772 ,  H05K2201/10893 ,  Y02P70/611 ,  Y02P70/613 ,  Y10T29/49126 ,  Y10T29/49147 ,  Y10T29/49149 ,  H01L2924/00 ,  H01L2924/00012

Abstract: An apparatus comprising a multi-layer substrate including a plurality of layers of insulative material, at least one well formed in at least one of the layers, the well extending from an outer surface of the multi-layer substrate to an inner surface of the multi-layer substrate, and an electrically conductive component formed within the well on the inner surface of the multi-layer substrate; and a device having at least one electrically conductive lead or wire extending into the well and being in direct physical contact with the electrically conductive component formed on the inner surface of the multi-layer substrate. Also, a method of manufacturing an apparatus comprising the steps of forming a multi-layer substrate including a plurality of layers of insulative material, at least one well formed in at least one of the layers, the well extending from an outer surface of the multi-layer substrate to an inner surface of the multi-layer substrate, and an electrically conductive component formed within the well on the inner surface of the multi-layer substrate; and extending at least one electrically conductive lead or wire from a device into the well such that the lead or wire is in direct physical contact with the electrically conductive component formed on the inner surface of the multi-layer substrate.

Abstract translation: 一种包括多层衬底的装置，所述多层衬底包括多层绝缘材料，至少一个阱形成在至少一层中，所述阱从所述多层衬底的外表面延伸到所述多层衬底的内表面 以及在所述多层基板的内表面上的所述阱内形成的导电部件; 以及具有延伸到阱中的至少一个导电引线或导线并与形成在多层基板的内表面上的导电部件直接物理接触的器件。 另外，制造装置的方法包括以下步骤：形成包括多层绝缘材料的多层基板，至少一层形成在至少一层中的阱，所述阱从多层的外表面延伸 在多层基板的内表面上形成有在多层基板的内表面上的导电部件， 并且将至少一个导电引线或线从器件延伸到阱中，使得引线或引线与形成在多层衬底的内表面上的导电部件直接物理接触。

公开(公告)号：WO9926460A8

公开(公告)日：1999-07-01

申请号：PCT/US9824251

申请日：1998-11-13

Applicant: PANDA PROJECT

Inventor： CRANE STANFORD W JR ,  KRISHNAPURA LAKSHMINARASIMHA ,  BEHAR MOISES ,  DUTTA ARINDUM ,  LINK KEVIN J ,  AHERN WILLIAM

IPC: H01L23/36 ,  H01L23/467 ,  H05K7/20

CPC classification number: H01L23/467 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A cooling system for a die carrier includes a cooling fan (742) disposed at a substantial distance from the semiconductor die carrier and a cooling duct (744) including an inlet portion (752) and an outlet portion (754). The cooling duct inlet portion (752) is attached to the cooling fan (742) and a heat exchanger (746) is disposed on an upper surface of the semiconductor die carrier (730). The cooling duct outlet portion (754) is disposed in close proximity to the heat exchanger (746) such that the cooling fan (742) draws ambient air into the cooling duct (744) and the ambient air exists the cooling duct outlet portion (754) and passes in a heat exchanger relationship with the heat exchanger (746).

Abstract translation: 用于模具载体的冷却系统包括设置在距离半导体管芯载体相当远的冷却风扇（742）和包括入口部分（752）和出口部分（754）的冷却管道（744）。 冷却管道入口部分（752）附接到冷却风扇（742），并且热交换器（746）设置在半导体管芯载体（730）的上表面上。 冷却管出口部分（754）设置在热交换器（746）附近，使得冷却风扇（742）将环境空气吸入冷却管道（744），并且环境空气存在于冷却管道出口部分（754） ）并与热交换器（746）的热交换器关系通过。

公开(公告)号：WO1996041378A1

公开(公告)日：1996-12-19

申请号：PCT/US1996009325

申请日：1996-06-04

Applicant: THE PANDA PROJECT

Inventor： THE PANDA PROJECT ,  MOSLEY, Joseph, M. ,  PORTUONDO, Maria, M.

IPC: H01L25/065

CPC classification number: H01L25/0657 ,  H01L2224/48091 ,  H01L2224/49109 ,  H01L2225/0651 ,  H01L2225/06582 ,  H01L2924/01004 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/1532 ,  H01L2924/16195 ,  H01L2924/19041 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A semiconductor die carrier includes an insulative package; a plurality of conductive leads extending from the insulative package; a die attach plate housed within the insulative package, the die attach plate comprising a first surface located on one side of the die attach plate and a second surface located opposite the first surface on an opposing side of the die attach plate; at least one semiconductor die secured to the first surface of the die attach plate; and at least one semiconductor die secured to the second surface of the die attach plate.

Abstract translation: 半导体管芯载体包括绝缘封装; 从所述绝缘封装延伸的多个导电引线; 所述管芯附接板包括位于所述管芯安装板的一侧的第一表面和与所述管芯附接板的相对侧相对的第二表面的第二表面; 至少一个半导体管芯固定到管芯附接板的第一表面; 以及至少一个半导体管芯，其固定到管芯附接板的第二表面。

公开(公告)号：WO9524729A3

公开(公告)日：1996-05-02

申请号：PCT/US9502676

申请日：1995-03-09

Applicant: PANDA PROJECT

Inventor： CRANE STANFORD W JR ,  PORTUONDO MARIA M ,  ERICKSON WILLARD ,  BIZZARRI MAURICE

IPC: G06F1/18 ,  G06F13/00 ,  G06F13/14 ,  G06F13/40 ,  G06F15/00 ,  G06F15/76 ,  G06F15/78 ,  H01R12/50 ,  H01R33/00 ,  H05K1/00 ,  H05K1/14 ,  H05K7/10 ,  H05K7/14 ,  H05K7/18 ,  H01L

CPC classification number: G06F1/185 ,  G06F1/184 ,  G06F1/186 ,  G06F13/4045 ,  G06F13/409 ,  H01R12/57 ,  H01R12/58 ,  H01R12/737 ,  H05K1/0286 ,  H05K1/14 ,  H05K7/1084 ,  H05K7/1441 ,  H05K7/1442 ,  H05K7/1444 ,  H05K7/1445

Abstract: A computeur system architecture in which functionally compatible electronic components are located on modular printed circuit boards. Thus, a type of processor used by the system can be changed by replacing the printed circuit board incorporating the processor. Similarly, a type of peripheral bus used can be changed simply by replacing the printed circuit board containing the peripheral controller. High-density connectors connect the circuit boards. Some embodiments of the invention use a single backplane. Other embodiments place peripheral slots on a second, passive backplane.

公开(公告)号：WO1995024733A1

公开(公告)日：1995-09-14

申请号：PCT/US1995002675

申请日：1995-03-09

Applicant: THE PANDA PROJECT

Inventor： THE PANDA PROJECT ,  CRANE, Stanford, W., Jr. ,  PORTUONDO, Maria, M.

IPC: H01L23/498

CPC classification number: H01L24/49 ,  H01L23/057 ,  H01L23/49827 ,  H01L23/49861 ,  H01L24/48 ,  H01L2224/45111 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45164 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48472 ,  H01L2224/49109 ,  H01L2224/49174 ,  H01L2224/49431 ,  H01L2224/49433 ,  H01L2224/85444 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01039 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/12044 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/16195 ,  H01L2924/181 ,  H05K1/182 ,  H05K1/183 ,  H05K3/3426 ,  Y10T29/49146 ,  Y10T29/49147 ,  Y10T29/49153 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: A semiconductor die carrier includes a plurality of electrically insulative side walls; a plurality of electrically conductive leads extending from at least one of the side walls, each of the leads being individually manufactured without use of a lead frame; a semiconductor die positioned such that the electrically conductive leads are disposed at one or more locations around the periphery of the die; and structure for providing electrical connection between the semiconductor die and corresponding ones of the electrically conductive leads. A method of manufacturing a semiconductor die carrier includes the steps of individually manufacturing a plurality of electrically conductive leads without use of a lead frame; extending a plurality of the electrically conductive leads from at least one of a plurality of electrically insulative side walls; positioning a semiconductor die such that the electrically conductive leads are disposed at one or more locations around the periphery of the die; and electrically connecting the semiconductor die to corresponding ones of the electrically conductive leads.

Abstract translation: 半导体管芯载体包括多个电绝缘侧壁; 从至少一个侧壁延伸的多个导电引线，每个引线在不使用引线框架的情况下单独制造; 半导体管芯，定位成使得导电引线设置在围绕芯片周边的一个或多个位置; 以及用于在半导体管芯和对应的导电引线之间提供电连接的结构。 制造半导体管芯载体的方法包括以下步骤：在不使用引线框的情况下分别制造多个导电引线; 从多个电绝缘侧壁中的至少一个延伸多个导电引线; 定位半导体管芯，使得导电引线设置在围绕芯片周边的一个或多个位置处; 并且将半导体管芯电连接到相应的导电引线。

公开(公告)号：WO1995024729A2

公开(公告)日：1995-09-14

申请号：PCT/US1995002676

申请日：1995-03-09

Applicant: THE PANDA PROJECT

Inventor： THE PANDA PROJECT ,  CRANE, Stanford, W., Jr. ,  PORTUONDO, Maria, M. ,  ERICKSON, Willard ,  BIZZARRI, Maurice

IPC: H01L00/00

CPC classification number: G06F1/185 ,  G06F1/184 ,  G06F1/186 ,  G06F13/4045 ,  G06F13/409 ,  H01R12/57 ,  H01R12/58 ,  H01R12/737 ,  H05K1/0286 ,  H05K1/14 ,  H05K7/1084 ,  H05K7/1441 ,  H05K7/1442 ,  H05K7/1444 ,  H05K7/1445

Abstract: A computeur system architecture in which functionally compatible electronic components are located on modular printed circuit boards. Thus, a type of processor used by the system can be changed by replacing the printed circuit board incorporating the processor. Similarly, a type of peripheral bus used can be changed simply by replacing the printed circuit board containing the peripheral controller. High-density connectors connect the circuit boards. Some embodiments of the invention use a single backplane. Other embodiments place peripheral slots on a second, passive backplane.

Abstract translation: 功能兼容的电子元件位于模块化印刷电路板上的计算系统架构。 因此，可以通过替换包含处理器的印刷电路板来改变系统使用的一种处理器。 类似地，可以简单地通过更换包含外围控制器的印刷电路板来改变所使用的一种外围总线。 高密度连接器连接电路板。 本发明的一些实施例使用单个背板。 其他实施例将外围插槽放置在第二无源底板上。

公开(公告)号：WO9926158B1

公开(公告)日：1999-07-08

申请号：PCT/US9824253

申请日：1998-11-13

Applicant: PANDA PROJECT

Inventor： CRANE STANFORD W JR ,  KRISHNAPURA LAKSHMINARASIMHA ,  FUOCO DANIEL ,  LEE ROY K ,  LINK KEVIN J ,  BEHAR MOISES ,  DUTTA ARINDUM ,  CROSS WILLIAM

IPC: G06F1/18 ,  G06F1/16 ,  G06F13/40 ,  H05K7/14

CPC classification number: G06F13/409

Abstract: A computer system includes a bus system; a pluggable central processing unit circuit board, coupled to the bus system; a pluggable logic board coupled to the pluggable central processing unit circuit board through the bus system; a pluggable input/output board coupled to the pluggable logic board through the bus system; a first connector unit for directly connecting the pluggable central processing unit circuit board to a first predetermined location on the pluggable logic board; and a second connector unit for directly connecting the pluggable logic board to a predetermined location on the pluggable input/output board.

Abstract translation: 计算机系统包括总线系统; 耦合到总线系统的可插拔中央处理单元电路板; 可插拔逻辑板，其通过总线系统耦合到可插拔中央处理单元电路板; 通过总线系统耦合到可插拔逻辑板的可插拔输入/输出板; 第一连接器单元，用于将可插拔中央处理单元电路板直接连接到可插拔逻辑板上的第一预定位置; 以及用于将可插拔逻辑板直接连接到可插拔输入/输出板上的预定位置的第二连接器单元。

公开(公告)号：WO1996041400A1

公开(公告)日：1996-12-19

申请号：PCT/US1996009282

申请日：1996-06-05

Applicant: THE PANDA PROJECT

Inventor： THE PANDA PROJECT ,  CRANE, Stanford, W., Jr. ,  PORTUONDO, Maria, M.

IPC: H01R13/26

CPC classification number: H01R13/11 ,  H01R12/716 ,  H01R13/26 ,  H01R24/60 ,  H01R2107/00

Abstract: An electrically conductive contact beam (6) for use in an electrical interconnect component. The contact beam (6) includes a stabilizing section (62) for securing the contact beam (6) within a support substrate (7) and a contact section (61), connected to the stabilizing section (62), for establishing contact between the contact beam (6) and an electrically conductive contact from another electrical interconnect component. The contact section includes a merge radius section connecting the contact section to the stabilizing section (62), a flexible section (61b) connected to the merge radius section (61a) and having an elongated curvature, a contact area (61c), disposed at an end of the curvature opposite the merge radius section (61a), for contacting the conductive contact from the other electrical interconnect component, and a lead-in section (61d), connected to the contact area (61c), for initiating deflection of the contact section (61) upon contact of the lead-in section (61d) with a portion of the other electrical interconnect component.

Abstract translation: 一种用于电互连部件的导电接触梁（6）。 接触梁（6）包括用于将接触梁（6）固定在支撑衬底（7）内的稳定部分（62）和连接到稳定部分（62）的接触部分（61），用于在 接触梁（6）和来自另一电互连部件的导电触头。 接触部分包括将接触部分连接到稳定部分（62）的合并半径部分，连接到合并半径部分（61a）并且具有细长曲率的柔性部分（61b），接触区域（61c） 与合并半径部分（61a）相对的曲率的端部，用于接触来自另一个电气互连部件的导电接触件，以及连接到接触区域（61c）的引入部分（61d），用于引起 接触部分（61）在导入部分（61d）与另一个电互连部件的一部分接触时。

公开(公告)号：WO1996041377A1

公开(公告)日：1996-12-19

申请号：PCT/US1996009277

申请日：1996-06-05

Applicant: THE PANDA PROJECT

Inventor： THE PANDA PROJECT ,  MOSLEY, Joseph, M. ,  PORTUONDO, Maria, M.

IPC: H01L23/64

CPC classification number: H01L24/49 ,  H01L23/49537 ,  H01L23/49548 ,  H01L23/49861 ,  H01L23/50 ,  H01L23/642 ,  H01L23/66 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/45111 ,  H01L2224/48011 ,  H01L2224/48091 ,  H01L2224/49109 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01043 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01072 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/1532 ,  H01L2924/16152 ,  H01L2924/16195 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K3/3421 ,  H01L2924/2065 ,  H01L2924/20651 ,  H01L2924/20652 ,  H01L2924/00 ,  H01L2224/45099

Abstract: A semiconductor die carrier includes an insulative module; a plurality of electrically conductive leads extending from the insulative module; a semiconductor die housed with the insulative module; and at least one high frequency capacitor secured to the insulative module for facilitating transmission of high frequency signals carried to and from the semiconductor die on the electrically conductive leads.

Abstract translation: 半导体管芯载体包括绝缘模块; 从所述绝缘模块延伸的多个导电引线; 与绝缘模块一起容纳的半导体管芯; 以及固定到绝缘模块的至少一个高频电容器，用于便于传输在导电引线上和从半导体管芯上传输的高频信号。