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公开(公告)号:EP4369383A1
公开(公告)日:2024-05-15
申请号:EP23201782.2
申请日:2023-10-05
申请人: NXP B.V.
IPC分类号: H01L21/56 , H01L23/13 , H01L23/538
CPC分类号: H01L23/13 , H01L23/5389 , H01L21/561
摘要: A method of forming a semiconductor device is provided. The method includes forming a first cavity at a first major surface of a first encapsulant. A first semiconductor die is affixed on the first major surface of the first encapsulant and a second semiconductor die is affixed on a bottom surface of the first cavity. A second encapsulant encapsulates the first semiconductor die, the second semiconductor die, and at least exposed portions of the first major surface of the first encapsulant. A package substrate is formed on a first major surface of the second encapsulant. The package substrate includes conductive traces interconnected to the first semiconductor die and the second semiconductor die.
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公开(公告)号:EP4367054A1
公开(公告)日:2024-05-15
申请号:EP22741235.0
申请日:2022-06-30
CPC分类号: B81C1/00396 , B81C1/00269 , B81C2203/01920130101 , H01L2224/8382520130101 , H01L2924/146120130101 , H01L2224/2914720130101 , H01L2224/2911120130101 , H01L2224/2908220130101 , H01L2224/8319320130101 , H01L2924/1515320130101 , H01L2224/3222520130101 , H01L2224/2901120130101 , H01L23/10 , H01L2224/3223820130101 , H01L2224/2746220130101 , H01L2224/838120130101 , H01L2224/3250320130101 , H01L2224/2914420130101 , H01L2224/2913920130101 , H01L2224/2915520130101 , H01L2224/9520130101 , H01L2224/9420130101 , H01L24/83 , H01L24/27 , H01L2224/274720130101 , H01L24/29 , H01L24/32 , H01L21/561
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公开(公告)号:EP4362071A2
公开(公告)日:2024-05-01
申请号:EP23206096.2
申请日:2023-10-26
发明人: GANI, David
IPC分类号: H01L21/60 , H01L23/538 , H01L21/56 , H01L23/31
CPC分类号: H01L24/19 , H01L24/96 , H01L23/5389 , H01L23/3128 , H01L21/561 , H01L21/568
摘要: The present disclosure is directed to at least one semiconductor package including a die (204) within an encapsulant (202) having a first sidewall, an adhesive layer (222) on the encapsulant and having a second sidewall coplanar with the first sidewall of the encapsulant, and an insulating layer (226) on the adhesive layer having a third sidewall coplanar with the first sidewall and the second sidewall. A method of manufacturing the at least one semiconductor package includes forming an insulating layer on a temporary adhesion layer of a carrier, forming an adhesive layer on the insulating layer, and forming a plurality of openings through the adhesive layer and the insulating layer. The plurality of openings through the adhesive layer and the insulating layer may be formed by exposing the adhesive layer and the insulating layer to a laser.
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公开(公告)号:EP3385984A1
公开(公告)日:2018-10-10
申请号:EP16869987.4
申请日:2016-11-30
发明人: LI, Yangyuan , DING, Shaobo
IPC分类号: H01L23/498 , H01L21/50
CPC分类号: H01L23/053 , H01L21/50 , H01L21/561 , H01L23/3121 , H01L23/498
摘要: Disclosed in the present invention are a sensor packaging structure and a manufacturing method thereof. The sensor packaging structure includes a protection board, a circuit structure and a filling structure. A front surface of the circuit structure is connected to a first surface of the protection board. A second surface of the protection board is used as a sensing function surface. The filling structure is located on the outer periphery of the circuit structure and connected to the first surface of the protection board. The circuit structure includes a chip and a substrate. The chip and the substrate are connected back to back. A front surface of the chip is located at the front surface of the circuit structure and is provided with a functional circuit. A front surface of the substrate is located at a back surface of the circuit structure and is provided with a pad. The pad is electrically connected to the functional circuit on the front surface of the chip. The sensor packaging structure of the present invention uses the protection board as a protection layer of the functional circuit, which can effectively protect the functional circuit of the sensor. Meanwhile, the protection board is first connected to the circuit structure in the manufacturing method to avoid tolerance accumulation, increasing the manufacturing accuracy of the protection layer.
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公开(公告)号:EP3051583B1
公开(公告)日:2018-09-19
申请号:EP13894643.9
申请日:2013-09-27
IPC分类号: H01L23/498 , H01L21/56
CPC分类号: H01L24/17 , H01L21/561 , H01L21/563 , H01L21/6836 , H01L21/78 , H01L23/3128 , H01L23/3142 , H01L23/49805 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L23/49838 , H01L23/49894 , H01L23/50 , H01L23/562 , H01L23/564 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/32 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/81 , H01L24/97 , H01L2221/68327 , H01L2221/6834 , H01L2224/0401 , H01L2224/05009 , H01L2224/05022 , H01L2224/05124 , H01L2224/05572 , H01L2224/11 , H01L2224/1134 , H01L2224/1146 , H01L2224/1147 , H01L2224/11849 , H01L2224/13012 , H01L2224/13014 , H01L2224/13016 , H01L2224/13076 , H01L2224/13082 , H01L2224/13111 , H01L2224/13113 , H01L2224/13116 , H01L2224/13139 , H01L2224/13147 , H01L2224/13155 , H01L2224/16055 , H01L2224/16105 , H01L2224/16225 , H01L2224/16227 , H01L2224/16237 , H01L2224/1713 , H01L2224/32225 , H01L2224/45015 , H01L2224/48091 , H01L2224/48106 , H01L2224/48227 , H01L2224/48235 , H01L2224/73204 , H01L2224/73265 , H01L2224/81 , H01L2224/81191 , H01L2224/81385 , H01L2224/814 , H01L2224/81815 , H01L2224/83 , H01L2224/83104 , H01L2224/85 , H01L2224/94 , H01L2224/97 , H01L2924/00 , H01L2924/00014 , H01L2924/01029 , H01L2924/014 , H01L2924/05442 , H01L2924/0665 , H01L2924/10253 , H01L2924/15311 , H01L2924/15321 , H01L2924/181 , H01L2924/186 , H01L2924/2064 , H01L2924/351 , H05K3/284 , H05K3/3436 , H05K2201/068 , H05K2201/09427 , H05K2201/10704 , H05K2201/10977 , H05K2203/0465 , H01L2924/00012 , H01L2924/01047 , H01L2224/45099 , H01L2924/207
摘要: In a semiconductor device (SP1) according to an embodiment, a solder resist film (first insulating layer, SR1) which is in contact with the base material layer, and a resin body (second insulating layer, 4) which is in contact with the solder resist film and the semiconductor chip, are laminated in between the base material layer (2CR) of a wiring substrate 2 and a semiconductor chip (3). In addition, a linear expansion coefficient of the solder resist film is equal to or larger than a linear expansion coefficient of the base material layer, and the linear expansion coefficient of the solder resist film is equal to or smaller than a linear expansion coefficient of the resin body. Also, the linear expansion coefficient of the base material layer is smaller than the linear expansion coefficient of the resin body. According to the above-described configuration, damage of the semiconductor device caused by a temperature cyclic load can be suppressed, and thereby reliability can be improved.
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公开(公告)号:EP2831930B1
公开(公告)日:2018-09-19
申请号:EP13722081.0
申请日:2013-03-22
IPC分类号: H01L33/00 , H01L33/62 , H01L21/56 , H01L33/32 , H01L33/52 , H01L33/38 , H01L23/00 , H01L21/683
CPC分类号: H01L33/52 , H01L21/561 , H01L21/6835 , H01L24/29 , H01L24/32 , H01L24/83 , H01L24/94 , H01L33/0025 , H01L33/007 , H01L33/0075 , H01L33/0079 , H01L33/32 , H01L33/382 , H01L33/387 , H01L33/62 , H01L2221/6835 , H01L2221/68377 , H01L2221/68381 , H01L2224/29076 , H01L2224/29144 , H01L2224/29186 , H01L2224/2919 , H01L2224/32227 , H01L2224/32235 , H01L2224/83005 , H01L2224/83007 , H01L2224/83192 , H01L2224/83815 , H01L2224/94 , H01L2924/01322 , H01L2924/12041 , H01L2924/12042 , H01L2933/0016 , H01L2933/005 , H01L2933/0066 , H01L2924/00 , H01L2924/0105 , H01L2224/83 , H01L2924/00014
摘要: A light-emitting device is described herein. The device includes a semiconductor structure comprising a III-nitride light emitting layer disposed between an n-type region and a p-type region. The device also includes a metal layer with openings formed therein and filled with an insulating material. The openings separate the metal layer into a first portion that is electrically isolated from a second portion. The first portion is coupled to the n-type region and the second portion coupled to the p-type region. The device also includes conductive stacks. A first surface of each of the conductive stacks contacts a surface of the metal layer opposite the semiconductor structure. A respective gap is positioned between each of the conductive stacks. A body is in direct contact with a second surface of each of the conductive stacks that is opposite the first surface.
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公开(公告)号:EP3367430A1
公开(公告)日:2018-08-29
申请号:EP18154192.1
申请日:2018-01-30
申请人: NXP B.V.
发明人: BUENNING, Hartmut
CPC分类号: H01L21/78 , H01L21/561 , H01L21/6836 , H01L23/293 , H01L23/3114 , H01L24/94 , H01L2221/68327 , H01L2221/6834
摘要: A method of manufacturing a device with six-sided protected walls is disclosed. The method includes fabricating the plurality of devices on a wafer, forming a plurality of contact pads on each of the plurality of devices, cutting a first trench around each of the plurality of devices from a backside of the wafer with an active side having a plurality of contact pads facing down, applying a protective coating on the backside of the wafer thus filling the first trench with a protective material of the protective coating on the backside and cutting a second trench from the active side. The second trench extends to end of the first trench; The method further includes applying a protective layer on the active side including filling the second trench with the material of the protective coating on the active side thus making a wall through a combination of the first trench and the second trench, the wall fully filled with the material of the protective layer on the backside and the protective layer on the active side and singulating each of the plurality of devices by cutting through the wall substantially in middle across a thickness of the wafer.
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公开(公告)号:EP2126971B1
公开(公告)日:2018-08-29
申请号:EP08713435.9
申请日:2008-01-03
申请人: Analog Devices, Inc.
CPC分类号: H01L23/3128 , H01L21/561 , H01L21/563 , H01L21/565 , H01L21/566 , H01L23/3107 , H01L23/3114 , H01L23/3121 , H01L23/3142 , H01L23/3171 , H01L23/3178 , H01L23/3185 , H01L2224/13022 , H01L2224/73203 , H01L2224/94 , H01L2924/00011 , H01L2924/00014 , H01L2924/01057 , H01L2924/01078 , H01L2924/01079 , H01L2924/10158 , H01L2224/0401 , H01L2224/03
摘要: An electronics package includes a wafer die substrate containing electronic circuits and having a top surface and a bottom surface. A top protective layer is substantially thinner than the substrate and covers the top surface. A bottom protective layer is substantially thinner than the substrate and covers the bottom surface. Circuit contacts are distributed about the bottom protective layer for electrically coupling the substrate electronic circuits to external electronic circuits.
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公开(公告)号:EP2406815B1
公开(公告)日:2018-07-18
申请号:EP10708971.6
申请日:2010-03-09
申请人: 3D Plus
发明人: VAL, Christian
IPC分类号: H01L21/56 , H01L23/00 , B81C1/00 , H01L23/433 , H01L21/683 , H01L25/065 , H01L25/10 , H01L25/00
CPC分类号: H01L21/568 , H01L21/561 , H01L21/6836 , H01L23/4334 , H01L24/24 , H01L24/96 , H01L24/97 , H01L25/0657 , H01L25/105 , H01L25/50 , H01L2221/68327 , H01L2224/24137 , H01L2224/24998 , H01L2224/32245 , H01L2224/73217 , H01L2224/92144 , H01L2224/97 , H01L2225/06527 , H01L2225/06551 , H01L2225/06589 , H01L2225/1023 , H01L2225/1064 , H01L2225/1094 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01057 , H01L2924/01058 , H01L2924/01061 , H01L2924/01074 , H01L2924/01075 , H01L2924/01079 , H01L2924/09701 , H01L2924/1461 , H01L2924/181 , H01L2924/18162 , H01L2224/83 , H01L2224/82 , H01L2924/00
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公开(公告)号:EP3232467A4
公开(公告)日:2018-07-11
申请号:EP14907653
申请日:2014-12-09
IPC分类号: H01L23/552 , H01L23/495
CPC分类号: H01L23/552 , H01L21/561 , H01L23/293 , H01L23/3107 , H01L23/4952 , H01L23/49541 , H01L23/49551 , H01L23/49582 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/73 , H01L24/97 , H01L2224/32245 , H01L2224/45124 , H01L2224/45144 , H01L2224/48247 , H01L2224/73265 , H01L2224/97 , H01L2924/181 , H01L2924/1815 , H01L2924/19107 , H01L2224/85 , H01L2224/83 , H01L2924/00012
摘要: A lead frame includes: a second terminal that is disposed to surround terminals on a package plane and can be grounded; and a conductive member that covers molded resin and is electrically connected to the second terminal.
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