公开(公告)号：EP2780940A4

公开(公告)日：2015-06-17

申请号：EP12850220

申请日：2012-11-13

Applicant: MICRON TECHNOLOGY INC

Inventor： LUO SHIJIAN ,  LI XIAO

IPC: H01L23/34 ,  H01L21/8242 ,  H01L23/36 ,  H01L23/367 ,  H01L23/373 ,  H01L23/42 ,  H01L25/065 ,  H01L25/18 ,  H01L27/108

CPC classification number: H01L23/36 ,  H01L23/3675 ,  H01L23/3677 ,  H01L23/3736 ,  H01L23/42 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2225/06589 ,  H01L2924/15311

Abstract: A semiconductor die assembly comprises a plurality of semiconductor dice in a stack. Another semiconductor die is adjacent to the stack and has a region, which may comprise a relatively higher power density region, extends peripherally beyond the stack. Conductive elements extend between and electrically interconnect integrated circuits of semiconductor dice in the stack and of the other semiconductor die. Thermal pillars are interposed between semiconductor dice of the stack, and a heat dissipation structure, such as a lid, is in contact with an uppermost die of the stack and the higher power density region of the other semiconductor die. Other die assemblies, semiconductor devices and methods of managing heat transfer within a semiconductor die assembly are also disclosed.

公开(公告)号：EP2720520A4

公开(公告)日：2015-05-27

申请号：EP12797274

申请日：2012-05-30

Applicant: KYOCERA CORP

Inventor： NAKAMURA KIYOTAKA ,  OHASHI YOSHIO ,  ABE YUUICHI ,  HIRANO EISUKE ,  SHIKATA KUNIHIDE ,  SEKIGUCHI KEIICHI

IPC: H05K1/11 ,  H01L23/13 ,  H01L23/14 ,  H05K1/09

CPC classification number: H05K1/09 ,  H01L23/15 ,  H01L23/3677 ,  H01L23/49827 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H05K1/0206 ,  H05K1/0306 ,  H05K1/115 ,  H05K3/4061 ,  H05K2201/0266 ,  H05K2201/0326 ,  H05K2203/049 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: [Problem] To provide a highly-reliable circuit board and an electronic device obtained by mounting electronic components on the circuit board, which have high bonding strength and excellent heat discharge properties, and can be used over a long period as a result of minimizing cavities in a metal wiring layer formed on a through conductor. [Solution] A circuit board (10) is provided with a through conductor (13) comprising a metal in a through hole (12) that penetrates in the thickness direction of a ceramic sintered body (11), and a metal wiring layer (14) that covers and is connected to the surface of the through conductor (13) on at least one main surface side of the ceramic sintered body (11). The through conductor (13) comprises: a first portion (13a) that is positioned on an inner wall side of the through hole (12), from one end to the other end of the through hole (12) in the thickness direction of the ceramic sintered body (11); and a second portion (13b) that adjoins the first portion (13a). The average crystal grain size in the second portion (13b) is larger than the average crystal grain size in the first portion (13a).

Abstract translation: [问题]提供一种高可靠性的电路板和通过将电子部件安装在电路板上而获得的电路板和电子器件，其具有高的接合强度和优异的散热性能，并且由于使空腔最小化，可以长时间使用 在形成在贯通导体上的金属布线层中。 电路板（10）在贯通陶瓷烧结体（11）的厚度方向的贯通孔（12）中设置贯通导体（13），该穿通导体（13）具有金属，金属配线层（14） ），其在陶瓷烧结体（11）的至少一个主表面侧覆盖并连接到贯通导体（13）的表面。 贯通导体（13）包括：第一部分（13a），其位于通孔（12）的内壁侧，从通孔（12）的一端到另一端沿着该通孔的厚度方向 陶瓷烧结体（11）; 和邻接第一部分（13a）的第二部分（13b）。 第二部分（13b）中的平均晶粒尺寸大于第一部分（13a）中的平均晶粒尺寸。

公开(公告)号：EP2857787A1

公开(公告)日：2015-04-08

申请号：EP14185010.7

申请日：2009-12-15

Applicant: Yang, Tai-Her

Inventor： Yang, Tai-Her

IPC: F28F13/00 ,  F28F21/08 ,  F28F23/00 ,  H01L23/36 ,  H01L23/367 ,  H01L23/373 ,  A47J27/00 ,  A47J27/022 ,  A47J36/02 ,  F28F13/18 ,  F28F13/14

CPC classification number: A47J36/02 ,  A47J27/002 ,  A47J27/022 ,  F28F13/00 ,  F28F13/14 ,  F28F13/18 ,  F28F21/08 ,  F28F23/00 ,  F28F2013/006 ,  H01L23/36 ,  H01L23/3677 ,  H01L23/373 ,  H01L23/3735 ,  H01L2924/0002 ,  Y10T428/13 ,  H01L2924/00

Abstract: The present invention relates to relay thermal conductor made of material having better thermal conductivity coefficient, wherein which is thermal conductively coupled with heating or cooling first thermal body at one end or face thereof, and is coupled with interface thermal conductor having higher specific heat capacity at the other end or face thereof; the relay thermal conductor directly performs thermal conduction with second thermal body at another part thereof; and the interface thermal conductor having higher specific heat capacity is the thermal conducting carrier between the relay thermal conductor and the second thermal body.

Abstract translation: 本发明涉及具有更好的热传导系数进行中继的材料制成的热导体，worin所有这一切都被热传导地耦合加热下，或者在一个端部冷却第一热体或面上，并且被耦合以在具有较高的比热容接口热导体 的另一端或面体; 中继热导体直接进行热传导，在其另一部分第二热体; 和具有较高的比热容的界面热导体是中继热导体和所述第二热体之间的导热载体。

公开(公告)号：EP2854168A2

公开(公告)日：2015-04-01

申请号：EP14184831.7

申请日：2014-09-15

Applicant: General Electric Company

Inventor： Chauhan, Shakti Singh ,  McConnelee, Paul Alan ,  Gowda, Arun Virupaksha

IPC: H01L23/00 ,  H01L23/538 ,  H05K1/18

CPC classification number: H01L23/5389 ,  H01L23/34 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/3736 ,  H01L23/42 ,  H01L23/433 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/53295 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/24 ,  H01L24/25 ,  H01L24/26 ,  H01L24/32 ,  H01L24/82 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/2402 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2224/24225 ,  H01L2224/2518 ,  H01L2224/2732 ,  H01L2224/27416 ,  H01L2224/291 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/8201 ,  H01L2224/82031 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2224/82101 ,  H01L2224/83005 ,  H01L2224/83132 ,  H01L2224/83192 ,  H01L2224/83855 ,  H01L2224/92144 ,  H01L2924/1203 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/1433 ,  H01L2924/15747 ,  H01L2924/15787 ,  H01L2924/181 ,  H05K1/0266 ,  H05K1/185 ,  H05K3/305 ,  H05K3/4602 ,  H05K3/4605 ,  H05K3/4688 ,  H05K2201/0187 ,  H05K2203/0278 ,  H05K2203/063 ,  H05K2203/166 ,  H01L2924/014 ,  H01L2924/00

Abstract: A package structure (10) includes a dielectric layer (14), at least one semiconductor device (12) attached to the dielectric layer (14), one or more dielectric sheets (26) applied to the dielectric layer (14) and about the semiconductor device(s) (12) to embed the semiconductor device(s) (12) therein, and a plurality of vias (30,36) formed to the semiconductor device(s) (12) that are formed in at least one of the dielectric layer (14) and the one or more dielectric sheets (26). The package structure (10) also includes metal interconnects (38) formed in the vias (30,36) and on one or more outward facing surfaces (18,20) of the package structure (10) to form electrical interconnections to the semiconductor device(s) (12). The dielectric layer (14) is composed of a material that does not flow during a lamination process and each of the one or more dielectric sheets (26) is composed of a curable material configured to melt and flow when cured during the lamination process so as to fill-in any air gaps around the semiconductor device(s) (12).

Abstract translation: 封装结构（10）包括电介质层（14），附着到电介质层（14）的至少一个半导体器件（12），施加到电介质层（14）上的一个或多个电介质片（26） 将半导体器件（12）嵌入其中的半导体器件（12）和形成在半导体器件（12）上的多个通孔（30,36），其形成在至少一个 电介质层（14）和一个或多个电介质片（26）。 封装结构（10）还包括形成在通孔（30,36）中的金属互连（38）和封装结构（10）的一个或多个向外表面（18,20）上，以形成与半导体器件 （12）。 电介质层（14）由在层压工艺期间不流动的材料构成，并且所述一个或多个电介质片（26）中的每一个由可在层压过程中固化时被熔化和流动的可固化材料构成，以便 以填充半导体器件（12）周围的任何气隙。

公开(公告)号：EP2792220A1

公开(公告)日：2014-10-22

申请号：EP12816702.0

申请日：2012-12-10

Applicant: Valeo Systèmes de Contrôle Moteur

Inventor： BENDANI, Larbi ,  ASKEUR, Mimoun ,  DELAPORTE, Francis

IPC: H05K1/02 ,  H01L23/367 ,  H05K7/20

CPC classification number: H05K3/28 ,  C25D11/00 ,  H01L23/3677 ,  H01L2924/0002 ,  H05K1/0204 ,  H05K1/021 ,  H05K1/0256 ,  H05K3/0061 ,  H05K2201/066 ,  H05K2201/10075 ,  H05K2201/1009 ,  H05K2201/10416 ,  H05K2203/0315 ,  H05K2203/0723 ,  H01L2924/00

Abstract: The invention relates to a method for producing a thermally conductive and electrically insulating link between at least one electronic component (2) and a completely or partially metal radiator (5), in which the electronic component (2) and the radiator (5) form part of an assembly (1) also comprising a printed circuit (4) disposed between the electronic component (2) and the radiator (5), said printed circuit (4) comprising at least one metal layer (8, 9) and a metal insert (13). According to the method, at least one metal surface (11, 12, 15, 16, 17) is anodised and the heat from the electronic component (2) is dissipated through said surface to the radiator (5), said metal surface belonging to one of the following: the electronic component (2), the printed circuit (4) or the radiator (5).

Abstract translation: 本发明涉及一种用于制造一个导热且电的至少一个电子元件（2）和一个完全呼叫或部分金属散热器（5），其中，所述电子部件（2）和散热器（5）的形式之间的绝缘链路 所述电子部件（2）和所述散热器之间设置较大的组件（1），以便包括印刷电路（4）的部分（5），所述印刷电路（4）包括至少一个金属层（8,9）和一个金属 插入（13）。 。根据该方法，至少一个金属表面（11，12，15，16，17）阳极化处理，并从电子部件的热量（2）通过所述表面消散到（5），所述金属表面属于该散热器 以下之一：所述电子部件（2），印刷电路（4）或散热器（5）。

公开(公告)号：EP2490255A4

公开(公告)日：2014-10-08

申请号：EP11814043

申请日：2011-05-06

Applicant: HUAWEI TECH CO LTD

Inventor： LUO BING ,  MARCONI FRANCO

IPC: H01L23/498 ,  H01L23/13 ,  H01L23/367

CPC classification number: H01L23/3677 ,  H01L23/13 ,  H01L23/66 ,  H01L2223/6627 ,  H01L2224/48227 ,  H05K1/021 ,  H05K1/0243 ,  H05K2201/09054

公开(公告)号：EP2780940A2

公开(公告)日：2014-09-24

申请号：EP12850220.0

申请日：2012-11-13

Applicant: Micron Technology, Inc.

Inventor： LUO, Shijian ,  LI, Xiao

IPC: H01L23/34 ,  H01L27/108 ,  H01L21/8242

CPC classification number: H01L23/36 ,  H01L23/3675 ,  H01L23/3677 ,  H01L23/3736 ,  H01L23/42 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2225/06589 ,  H01L2924/15311

Abstract: A semiconductor die assembly comprises a plurality of semiconductor dice in a stack. Another semiconductor die is adjacent to the stack and has a region, which may comprise a relatively higher power density region, extends peripherally beyond the stack. Conductive elements extend between and electrically interconnect integrated circuits of semiconductor dice in the stack and of the other semiconductor die. Thermal pillars are interposed between semiconductor dice of the stack, and a heat dissipation structure, such as a lid, is in contact with an uppermost die of the stack and the higher power density region of the other semiconductor die. Other die assemblies, semiconductor devices and methods of managing heat transfer within a semiconductor die assembly are also disclosed.

公开(公告)号：EP2780939A2

公开(公告)日：2014-09-24

申请号：EP12849421.8

申请日：2012-11-12

Applicant: Micron Technology, Inc.

Inventor： GROOTHUIS, Steven, K. ,  LI, Jian ,  ZHANG, Haojun ,  SILVESTRI, Paul, A. ,  LI, Xiao ,  LUO, Shijian ,  ENGLAND, Luke, G. ,  KEETH, Brent ,  GANDHI, Jaspreet, S.

IPC: H01L23/34 ,  H01L23/367

CPC classification number: H01L23/36 ,  H01L23/3675 ,  H01L23/3677 ,  H01L23/3736 ,  H01L23/42 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2225/06589 ,  H01L2924/15311

Abstract: Stacked semiconductor die assemblies with multiple thermal paths and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a plurality of first semiconductor dies arranged in a stack and a second semiconductor die carrying the first semiconductor dies. The second semiconductor die can include a peripheral portion that extends laterally outward beyond at least one side of the first semiconductor dies. The semiconductor die assembly can further include a thermal transfer feature at the peripheral portion of the second semiconductor die. The first semiconductor dies can define a first thermal path, and the thermal transfer feature can define a second thermal path separate from the first semiconductor dies.

公开(公告)号：EP2306512B1

公开(公告)日：2014-09-03

申请号：EP11150797.6

申请日：2006-07-05

Applicant: KABUSHIKI KAISHA TOYOTA JIDOSHOKKI ,  SHOWA DENKO KABUSHIKI KAISHA

Inventor： Otoshi, Kota ,  Kono, Eiji ,  Toh, Keiji ,  Tanaka, Katsufumi ,  Furukawa, Yuichi ,  Yamauchi, Shinobu ,  Hoshino, Ryoichi ,  Wakabayashi, Nobuhiro ,  Nakagawa, Shintaro

IPC: H01L23/36 ,  H01L23/367 ,  H01L23/373 ,  H01L23/473 ,  H05K1/02 ,  H05K3/34 ,  H05K3/00 ,  H05K1/03

CPC classification number: H05K3/0061 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/3735 ,  H01L23/473 ,  H01L2924/0002 ,  H05K1/0306 ,  H05K3/341 ,  H05K2201/0373 ,  H05K2201/1028 ,  H05K2203/0405 ,  Y02P70/613 ,  H01L2924/00

公开(公告)号：EP2763518A1

公开(公告)日：2014-08-06

申请号：EP12835560.9

申请日：2012-09-25

Applicant: Fujikura, Ltd.

Inventor： UETA, Nobuki

IPC: H05K3/46 ,  H01L23/12 ,  H01L23/36 ,  H05K1/02

CPC classification number: H05K1/185 ,  H01L23/3121 ,  H01L23/3677 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/5389 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/01327 ,  H05K1/0206 ,  H05K1/0298 ,  H05K1/186 ,  H05K3/0026 ,  H05K3/301 ,  H05K3/4038 ,  H05K3/4053 ,  H05K3/429 ,  H05K3/4614 ,  H05K3/4617 ,  H05K3/462 ,  H05K3/4623 ,  H05K2203/1453 ,  Y10T29/4913 ,  H01L2924/00

Abstract: A component built-in board mounting body(100) has a component built-in board(1) mounted on a mounting surface(2a) of a mounting board (2), the component built-in board(1) being configured having stacked therein a plurality of printed wiring bases (10, 20, 30, 40) that each have a wiring pattern and a via formed on/in a resin base(11, 21, 31, 41) thereof, and the component built-in board(1) being configured having an electronic component(90) built in thereto, wherein the component built-in board (1) has at least a portion of the plurality of printed wiring bases (10, 20, 30, 40) including thermal wiring (13, 23, 33, 43) in the wiring pattern and including a thermal via (14, 24, 34, 44) in the via, and the component built-in board(1) is mounted on the mounting board (2) via a bump (49) formed on a surface layer of the component built-in board (1), and a surface (91a) on an opposite side to an electrode formation surface(91b) of the built in electronic component(90) is connected to the bump(49) via the thermal via(14) and the thermal wiring (13), and is thermally connected to the mounting board (2) via the bump(49).