公开(公告)号：EP0510969A3

公开(公告)日：1993-03-03

申请号：EP92303655.2

申请日：1992-04-23

申请人： Tsubouchi, Kazuo

发明人： Tsubouchi, Kazuo ,  Ohmi, Tadahiro ,  Hiura, Yohei ,  Masu, Kazuya

IPC分类号： H01L23/532

CPC分类号： H01L23/53214 ,  H01L23/53228 ,  H01L23/53257 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor circuit device wiring is provided in which the wiring connected to a semiconductor element is composed of a crystalline material. The crystal axis direction along which nearest neighboring atoms in a single crystal constituting the crystalline material are arranged and the electric current direction through the wiring are crossed with each other at an angle of 22.5° or less.

公开(公告)号：EP3293760A1

公开(公告)日：2018-03-14

申请号：EP17178522.3

申请日：2017-06-28

申请人： Nexperia B.V.

发明人： Yeung, Shun Tik ,  Umali, Pompeo v ,  Leung, Chi Ho ,  Lam, Kan Wae

IPC分类号： H01L23/485 ,  H01L21/60 ,  H01L21/78

CPC分类号： H01L23/3114 ,  H01L21/2885 ,  H01L21/565 ,  H01L21/6836 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/78 ,  H01L23/147 ,  H01L23/3121 ,  H01L23/3185 ,  H01L23/49838 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/552 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/32 ,  H01L24/83 ,  H01L24/96 ,  H01L2224/02371 ,  H01L2224/03002 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/03462 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/04105 ,  H01L2224/05022 ,  H01L2224/05147 ,  H01L2224/05548 ,  H01L2224/05582 ,  H01L2224/05611 ,  H01L2224/0615 ,  H01L2224/10145 ,  H01L2224/26145 ,  H01L2224/2929 ,  H01L2224/32225 ,  H01L2224/838 ,  H01L2224/8385 ,  H01L2224/9202 ,  H01L2224/94 ,  H01L2224/03 ,  H01L2924/00014 ,  H01L2224/83

摘要： A semiconductor device includes a semiconductor die having a top surface that has one or more electrical contacts formed thereon, and an opposite bottom surface. A molding material encapsulates the top surface and at least a part of a side surface of the semiconductor die. The molding material defines a package body that has a top surface and a side surface. Openings are formed on the top surface of the package body, and the electrical contacts are partially exposed from the molding material through the openings. A metal layer is formed over and electrically connected to the electrical contacts through the openings. The metal layer extends to and at least partially covers the side surface of the package body.

摘要翻译： 一种半导体器件包括半导体管芯，该半导体管芯具有其上形成有一个或多个电触点的顶表面以及相对的底表面。 模制材料封装半导体管芯的顶表面和至少一部分侧表面。 模制材料限定具有顶表面和侧表面的封装体。 开口形成在封装体的顶表面上，并且电触头通过开口从模塑材料部分暴露。 金属层形成在电触点上并通过开口电连接到电触点。 金属层延伸并至少部分地覆盖封装体的侧表面。

公开(公告)号：EP3076431A4

公开(公告)日：2017-08-09

申请号：EP14865393

申请日：2014-11-26

申请人： ROHM CO LTD

发明人： NAGAO KATSUHISA ,  KAWAMOTO NORIAKI

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L29/12 ,  H01L29/739 ,  H01L29/78

CPC分类号： H01L27/11898 ,  H01L23/528 ,  H01L23/53214 ,  H01L23/53219 ,  H01L23/53228 ,  H01L23/53233 ,  H01L27/11807 ,  H01L27/11896 ,  H01L29/0615 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/4236 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/7395 ,  H01L29/7397 ,  H01L29/78 ,  H01L29/7803 ,  H01L29/7811 ,  H01L29/7813 ,  H01L2027/11866

摘要： A semiconductor device (1) is manufactured which includes a SiC epitaxial layer (28), a plurality of transistor cells (18) that are formed in the SiC epitaxial layer (28) and that are subjected to ON/OFF control by a predetermined control voltage, a gate electrode (19) that faces a channel region (32) of the transistor cells (18) in which a channel is formed when the semiconductor device (1) is in an ON state, a gate metal (44) that is exposed at the topmost surface for electrical connection with the outside and that is electrically connected to the gate electrode (19) while being physically separated from the gate electrode (19), and a built-in resistor (21) that is made of polysilicon and that is disposed below the gate metal (44) so as to electrically connect the gate metal (44) and the gate electrode (19) together.

摘要翻译： 制造包括SiC外延层（28），在SiC外延层（28）中形成的多个晶体管单元（18）并且通过预定控制进行开/关控制的半导体器件（1） 电压;栅极电极（19），其在半导体装置（1）处于导通状态时与形成有沟道的晶体管单元（18）的沟道区域（32）相对;栅极金属（44） 暴露在最外表面处以与外部电连接并且在与栅电极（19）物理分离的同时电连接到栅电极（19），以及内置电阻器（21），其由多晶硅制成并且 其设置在栅极金属（44）下方以将栅极金属（44）和栅极电极（19）电连接在一起。

公开(公告)号：EP3050080A4

公开(公告)日：2017-06-14

申请号：EP14847829

申请日：2014-09-25

申请人： INTEL CORP

发明人： CLARKE JAMES S ,  SCHMITZ ANTHONY C ,  SCHENKER RICHARD E

IPC分类号： H01L21/768 ,  H01L23/532

CPC分类号： H01L23/481 ,  H01L21/76816 ,  H01L21/76834 ,  H01L21/76838 ,  H01L21/76879 ,  H01L21/76883 ,  H01L21/76897 ,  H01L23/53228 ,  H01L23/53242 ,  H01L23/53257 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit and a method of forming an integrated circuit including a first dielectric layer including a surface, a plurality of first trenches defined in the dielectric layer surface, and a plurality of first wires, wherein each of the first wires are formed in each of the first trenches. The integrated circuit also includes a plurality of second trenches defined in the dielectric layer surface, and a plurality of second wires, wherein each of the second wires are formed in each of the second trenches. Further, the first wires comprise a first material having a first bulk resistivity and the second wires comprise a second material having a second bulk resistivity, wherein the first bulk resistivity and the second bulk resistivity are different.

摘要翻译： 集成电路和形成集成电路，其包括第一电介质层包括表面，在电介质层表面限定的第一沟槽的多个，并且第一线的多个，worin每个第一导线中的方法形成在每个的 第一沟槽。 因此，该集成电路包括在介电层表面限定的第二沟槽多个，并且第二导线复数，worin每个第二导线形成在每个所述第二沟槽。 此外，第一导线包括具有第一体电阻率的第一材料和所述第二导线包括具有第二材料的第二体电阻率，worin第一体电阻率和所述第二体电阻率是不同的。

公开(公告)号：EP3128042A1

公开(公告)日：2017-02-08

申请号：EP16182477.6

申请日：2016-08-02

申请人： Rohm and Haas Electronic Materials LLC ,  Dow Global Technologies LLC

发明人： THORSETH, Matthew ,  NIAZIMBETOVA, Zuhra ,  QIN, Yi ,  WOERTINK, Julia ,  DZIEWISZEK, Joanna ,  REDDINGTON, Erik ,  LEFEBVRE, Mark

IPC分类号： C25D3/38 ,  C25D5/02 ,  C25D7/00

CPC分类号： C25D3/38 ,  C25D5/022 ,  C25D7/00 ,  C25D7/12 ,  C25D7/123 ,  G03F7/405 ,  H01L21/76879 ,  H01L23/5226 ,  H01L23/53228 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/03462 ,  H01L2224/05147 ,  H01L2224/11 ,  H01L2224/11462 ,  H01L2224/13147 ,  H05K1/11 ,  H05K3/064 ,  H05K3/4007 ,  H05K2201/09209 ,  H01L2924/00012

摘要： Electroplating methods enable the plating of photoresist defined features which have substantially uniform morphology. The electroplating methods include copper electroplating baths with reaction products of imidazole and bisepoxides to electroplate the photoresist defined features. Such features include pillars, bond pads and line space features.

摘要翻译： 电镀方法能够限定光致抗蚀剂特征具有基本上均一的形态的镀覆。 电镀方法包括用咪唑的反应产物的铜电镀浴和双环氧化物电镀光刻胶限定的特征。 搜索功能包括支柱，焊盘和线路的空间功能。

公开(公告)号：EP3070739A3

公开(公告)日：2016-12-07

申请号：EP16153575.2

申请日：2016-02-01

申请人： MediaTek, Inc

发明人： SYU, Shih-Yi ,  HSIEH, Tung-Hsien ,  CHOU, Che-Ya

IPC分类号： H01L23/522 ,  H01L23/538 ,  H01L23/485 ,  H01L23/31 ,  H01L23/66

CPC分类号： H01L23/5386 ,  H01L23/291 ,  H01L23/3171 ,  H01L23/3192 ,  H01L23/49811 ,  H01L23/49838 ,  H01L23/5226 ,  H01L23/525 ,  H01L23/53228 ,  H01L23/5384 ,  H01L23/66 ,  H01L24/05 ,  H01L24/09 ,  H01L24/17 ,  H01L24/20 ,  H01L24/24 ,  H01L24/25 ,  H01L24/96 ,  H01L25/0655 ,  H01L2224/02331 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05008 ,  H01L2224/05013 ,  H01L2224/05015 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05553 ,  H01L2224/05555 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/12105 ,  H01L2224/13147 ,  H01L2224/19 ,  H01L2224/24137 ,  H01L2224/244 ,  H01L2224/245 ,  H01L2224/25175 ,  H01L2224/73209 ,  H01L2924/01029 ,  H01L2924/14 ,  H01L2924/18162 ,  H01L2924/3025 ,  H01L2924/00012 ,  H01L2924/00014

摘要： An RDL structure on a passivation layer includes a first landing pad disposed directly above a first on-chip metal pad; a first via in a passivation layer to electrically connecting the first landing pad with the first on-chip metal pad; a second landing pad disposed directly above the second on-chip metal pad; a second via in the passivation layer to electrically connecting the second landing pad with the second on-chip metal pad; and at least five traces being disposed on the passivation layer and passing through a space between the first landing pad and the second landing pad.

摘要翻译： 钝化层上的RDL结构包括直接设置在第一片上金属焊盘上方的第一焊盘; 在钝化层中的第一通孔，以将所述第一连接焊盘与所述第一片上金属焊盘电连接; 直接设置在所述第二片上金属焊盘之上的第二焊盘; 在所述钝化层中的第二通孔，以将所述第二着陆焊盘与所述第二片上金属焊盘电连接; 并且至少五条迹线设置在钝化层上并且穿过第一连接焊盘和第二连接焊盘之间的空间。

公开(公告)号：EP3050081A1

公开(公告)日：2016-08-03

申请号：EP14849833.0

申请日：2014-09-25

申请人： Intel Corporation

发明人： YOO, Hui Jae ,  INDUKURI, Tejaswi K. ,  CHEBIAM, Ramanan V. ,  CLARKE, James S.

IPC分类号： H01L21/28 ,  H01L21/60

CPC分类号： H01L21/76849 ,  H01L21/76838 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/76882 ,  H01L23/53209 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/53242 ,  H01L23/53252 ,  H01L23/53257 ,  H01L23/53266 ,  H01L2224/45015 ,  H01L2924/0002 ,  H01L2924/00011 ,  H01L2924/00

摘要： A dielectric layer and a method of forming thereof. An opening defined in a dielectric layer and a wire deposited within the opening, wherein the wire includes a core material surrounded by a jacket material, wherein the jacket material exhibits a first resistivity &rgr;1 and the core material exhibits a second resistivity &rgr;2 and &rgr;2 is less than &rgr;1.

摘要翻译： 电介质层及其形成方法。 限定在介电层中的开口和沉积在开口内的电线，其中所述电线包括由护套材料围绕的芯材料，其中所述护套材料表现出第一电阻率1，并且所述芯材料表现出第二电阻率 和＆rgr; 2小于＆rgr; 1。

公开(公告)号：EP1146558B1

公开(公告)日：2016-06-01

申请号：EP01300116.9

申请日：2001-01-08

申请人： Fujitsu Semiconductor Limited

发明人： Otsuka, Satoshi ,  Yamanoue, Akira

IPC分类号： H01L23/532 ,  H01L23/522 ,  H01L21/768 ,  H01L23/528

CPC分类号： H01L21/76816 ,  H01L21/76807 ,  H01L23/5226 ,  H01L23/53228 ,  H01L2924/0002 ,  H01L2924/00

公开(公告)号：EP2784181B1

公开(公告)日：2015-12-09

申请号：EP13161330.9

申请日：2013-03-27

申请人： Atotech Deutschland GmbH

发明人： Brüning, Frank, Dr. ,  Beck, Birgit ,  Etzkorn, Johannes, Dr. ,  Merschky, Michael, Dr. ,  Lowinski, Christian ,  Schulze, Jörg ,  Langhammer, Elisa

IPC分类号： C23C18/40

CPC分类号： C23C18/40 ,  C23C18/1639 ,  C23C18/405 ,  H01L21/76879 ,  H01L23/53228 ,  H01L2924/0002 ,  H01L2924/00

公开(公告)号：EP2863431A2

公开(公告)日：2015-04-22

申请号：EP15150443.8

申请日：2003-07-24

申请人： Fujitsu Semiconductor Limited

发明人： Watanabe, Kenichi

IPC分类号： H01L23/522 ,  H01L23/532 ,  H01L23/58 ,  H01L23/528

CPC分类号： H01L21/76877 ,  H01L21/76804 ,  H01L21/76843 ,  H01L23/481 ,  H01L23/485 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/5227 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53204 ,  H01L23/53223 ,  H01L23/53228 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295 ,  H01L23/562 ,  H01L23/58 ,  H01L23/585 ,  H01L29/0607 ,  H01L29/0611 ,  H01L29/0619 ,  H01L2924/0002 ,  H01L2924/00

摘要： There is provided a semiconductor device comprising: a rectangular semiconductor substrate including a semiconductor circuit region and four corners; a first insulating film formed above the rectangular semiconductor substrate; a second insulating film formed above the first insulating film; a plurality of guard rings which surround the semiconductor circuit region; and a first conductive layer formed in the first insulating film. Each of the guard rings comprises a groove-shaped via formed in the second insulating film and connected to the first conductive layer. The groove-shaped via includes a pattern bent twice each time at an angle of larger than 90 degree at each of the four corners, and the pattern is bent totally at 90 degree at each of the four corners of the semiconductor substrate.

摘要翻译： 提供了一种半导体器件，包括：包括半导体电路区和四个角的矩形半导体衬底; 形成在矩形半导体衬底上方的第一绝缘膜; 形成在第一绝缘膜上方的第二绝缘膜; 多个保护环，其围绕半导体电路区域; 以及形成在第一绝缘膜中的第一导电层。 每个保护环包括形成在第二绝缘膜中并连接到第一导电层的槽形通路。 槽形通孔包括在四个角的每一个处以大于90度的角度每次弯曲两次的图案，并且图案在半导体基板的四个角的每一个处均以90度完全弯曲。