公开(公告)号：EP0997942A3

公开(公告)日：2001-05-09

申请号：EP99308590.1

申请日：1999-10-29

Applicant: SHINKO ELECTRIC INDUSTRIES CO. LTD.

Inventor： Horiuchi, Michio, Shinko Electric Indust.,Co. Ltd. ,  Imai, Kazunari, Shinko Electric Indust.,Co. Ltd.

IPC: H01L23/498

CPC classification number: H01L23/49827 ,  H01L23/3114 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01322 ,  H01L2924/15174 ,  H01L2924/15311 ,  H05K3/3473 ,  H05K3/4038 ,  H05K3/423 ,  H05K2201/0305 ,  H05K2201/0355 ,  H05K2201/0394 ,  H05K2203/0733 ,  H01L2224/05599

Abstract: A semiconductor device that meets the demand for realizing semiconductor chips in small sizes has connection lands (20) formed on an electrode terminal carrying surface of a semiconductor chip (10) which are electrically connected via a substrate (12) and solder bumps (26) to an external circuit. The connection lands (20) are electrically connected, through connection bumps (14), to connection pads (22) formed on one surface of the interposing substrate (12) of an insulating material so as to face the connection lands (20). Conductor wiring patterns (24) inclusive of the connection pads (22) are formed on one surface of the interposing substrate (12). Conductor wiring patterns (30) inclusive of terminal lands on which the external connection terminals (26) will be mounted, are formed on the other surface of the interposing substrate (12). Conductor wiring patterns (24) formed on the one surface of the interposing substrate (12) are connected to the conductor wiring patterns (30) formed on the other surface of the interposing substrate (12) through solid vias (32) formed by filling recesses with a metal by plating. The recesses are formed to penetrate through the insulating material of the interposing substrate (12) by laser machining and this permits the back surfaces of the conductor wiring patterns (24) on the side of the insulating material to be exposed on their bottom surfaces so that these can be used as electrodes during the metal plating process.

公开(公告)号：EP1011139A4

公开(公告)日：2001-03-28

申请号：EP98905817

申请日：1998-03-09

Applicant: IBIDEN CO LTD

Inventor： TAKADA MASARU ,  MINOURA HISASHI ,  TSUKADA KIYOTAKA ,  KOBAYASHI HIROYUKI ,  KONDO MITSUHIRO

IPC: H05K3/00 ,  H01L23/12 ,  H01L23/498 ,  H01L23/50 ,  H05K1/11 ,  H05K3/28 ,  H05K3/34 ,  H05K3/38 ,  H05K3/46

CPC classification number: H01L24/49 ,  H01L23/49822 ,  H01L23/50 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49109 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/351 ,  H05K1/021 ,  H05K1/113 ,  H05K1/114 ,  H05K3/0035 ,  H05K3/28 ,  H05K3/3457 ,  H05K3/385 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4652 ,  H05K3/4697 ,  H05K2201/0355 ,  H05K2201/0394 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/09527 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2203/0315 ,  H05K2203/0554 ,  H05K2203/1581 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: In a printed wiring board, an odd number (n) of conductive layers (11-13) and insulating layers (21-23) are alternately laminated upon another. The first conductive layer (11) is constituted as a parts connecting layer and the n-th conductive layer (13) is constituted as an external connecting layer which is connected to external connecting terminals (7). The second to (n-1)-th conductive layers (12) are constituted as current transmitting layers for transmitting internal currents. The surface of the n-th conductive layer (13) is coated with the outermost n-th insulating layer (23) in a state where the external connecting terminals (7) are exposed on the surface. It is preferable to constitute the internal insulating layers of a glass-cloth reinforced prepreg and the external insulating layers of a resin.

公开(公告)号：EP1062634A1

公开(公告)日：2000-12-27

申请号：EP00900614.9

申请日：2000-01-19

Applicant: BULL CP8

Inventor： CARPIER, Roland ,  LAUVERNIER, Christine ,  LE LOC'H, Alain

IPC: G06K19/077

CPC classification number: G06K19/07769 ,  G06K19/07749 ,  G06K19/0775 ,  H01L2224/48227 ,  H01L2924/01057 ,  H01L2924/01078 ,  H05K1/112 ,  H05K1/183 ,  H05K3/3436 ,  H05K2201/0394 ,  H05K2201/09472 ,  H05K2201/10477 ,  H05K2203/0465 ,  Y02P70/613

Abstract: The invention concerns a chip card comprising a base body consisting of electrically insulating layers, the card bearing on one of its layers an open-loop antenna (6) having two ends, said body being provided with a cavity housing a micromodule (1) designed to be connected to said open-loop antenna by two terminals (31, 32), said micromodule comprising an electrically insulating support (2) bearing, on one first surface, a semiconductor component (3) and, on a second surface, several electric contact pads. The invention is characterised in that two contact pads (22, 23) are arranged in a strip passing through a central region of the support, said terminals being connected to said two contact pads respectively through said support, the two contact pads being connected to the antenna two ends respectively.

公开(公告)号：EP1014096A2

公开(公告)日：2000-06-28

申请号：EP99310179.9

申请日：1999-12-17

Applicant: SHINKO ELECTRIC INDUSTRIES CO. LTD.

Inventor： Muramatsu, Shigetsugu ,  Horiuchi, Michio ,  Kazama, Takuya

IPC: G01R1/04

CPC classification number: H05K1/112 ,  G01R31/2886 ,  H01L2224/16237 ,  H05K1/0393 ,  H05K3/06 ,  H05K3/325 ,  H05K2201/0394 ,  H05K2201/09472 ,  H05K2201/10734

Abstract: A substrate (50) is used for inspecting an electronic device (40) having bump-shaped connection terminals (42), and is used for an electrical test on the electronic device (40). The substrate includes opening sections (11), the diameter of which are determined so that a connection terminal (42) can be inserted into and drawn out from the opening (11), which are formed in a region on one side of an insulating substrate (10). The substrate (10) has an arrangement of connection terminals (20); and wiring patterns (14, 16) which corresponds to those of the electronic device (40). Each of the wiring patterns is composed of a pad section (16) exposed on a bottom face of the opening (11) so that the pad (16) can come into contact with the connection terminal (42) to accomplish electrical continuity, a connecting pad section (20) which is formed in a region outside of the region in which the pad section (16) is formed, and which comes into contact with a contact terminal (35) of an inspection device so as to accomplish electrical continuity, and a wiring section (14) for electrically connecting the pad section (16) with the connecting pad section (20). The wiring patterns (14, 16, 20) are formed on the other side of the insulating substrate (10).

Abstract translation: 基板（50）用于检查具有凸起状连接端子（42）的电子设备（40），并用于电子设备（40）的电气测试。 衬底包括开口部分（11），其直径被确定为使得可以将连接端子（42）插入并从开口（11）中拉出，该开口部分形成在绝缘衬底的一侧的区域中 （10）。 基板（10）具有连接端子（20）的布置。 以及对应于电子设备（40）的布线图案（14,16）。 每个布线图案由露出在开口（11）的底面上的垫部分（16）组成，使得垫（16）可以与连接端子（42）接触以实现电连续性，连接 衬垫部分（20），其形成在形成有所述衬垫部分（16）的区域的外侧的区域中，并且与所述检查装置的接触端子（35）接触以实现电连续性;以及 用于将焊盘部分（16）与连接焊盘部分（20）电连接的接线部分（14）。 布线图案（14,16,20）形成在绝缘基板（10）的另一侧。

公开(公告)号：EP0793405A3

公开(公告)日：1998-12-02

申请号：EP97301300

申请日：1997-02-27

Applicant: CTS CORP

Inventor： ERNSBERGER CRAIG N ,  LEACH SARAH E ,  ALLEN KATHLEEN E ,  WENZEL RALPH J ,  MEYER RICHARD C

IPC: C09D1/00 ,  C08L63/00 ,  C09D5/24 ,  H01B1/22 ,  H01L21/48 ,  H01L23/498 ,  H05K1/09 ,  H05K3/24 ,  H05K3/38 ,  H05K3/40 ,  H05K3/46

CPC classification number: H05K3/462 ,  H01B1/22 ,  H01L21/4857 ,  H01L23/49883 ,  H01L2924/0002 ,  H01L2924/09701 ,  H05K1/095 ,  H05K3/246 ,  H05K3/386 ,  H05K3/4069 ,  H05K3/4623 ,  H05K2201/0347 ,  H05K2201/0355 ,  H05K2201/0394 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/10378 ,  H05K2203/1131 ,  H05K2203/1453 ,  H05K2203/1461 ,  H01L2924/00

Abstract: Electronic assemblies comprising a sinterable composition are disclosed. The composition sinters reactively and/or non-reactively during the lamination cure cycle of the assembly. The composition generally comprises (i) at least one high melting particulate phase material, (ii) at least one low melting material, and (iii) an organic portion comprising a resin and a cross-linking agent.

公开(公告)号：EP0649565B1

公开(公告)日：1998-09-30

申请号：EP93912615.7

申请日：1993-06-24

Applicant: ROBERT BOSCH GMBH

Inventor： ROETHLINGSHOEFER, Walter ,  GOEBELS, Ulrich

IPC: H01L25/16 ,  H01L23/14 ,  H01L23/373

CPC classification number: H05K1/021 ,  H01L23/142 ,  H01L23/3677 ,  H01L23/3735 ,  H01L23/49833 ,  H01L24/45 ,  H01L24/48 ,  H01L25/16 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/0102 ,  H01L2924/14 ,  H01L2924/19041 ,  H05K1/0306 ,  H05K1/141 ,  H05K1/182 ,  H05K3/328 ,  H05K3/4084 ,  H05K2201/0355 ,  H05K2201/0394 ,  H05K2203/049 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/01005 ,  H01L2924/01034 ,  H01L2224/45147

Abstract: The proposal is for a fitting unit for a multilayer hybrid circuit (5) with power components (10) which facilitates very good heat dissipation from its semiconductor power components (10). To this end, the multilayer hybrid circuit (5) is fitted on a heat conductive baseboard (1; 1a), where the baseboard (1) is a ceramic plate covered with copper foil (3) or a ceramic-coated copper foil.

Abstract translation: PCT No.PCT / DE93 / 00548 Sec。 371日期1994年12月9日第 102（e）日期1994年12月9日PCT Filed 1993年6月24日PCT公布。 公开号WO94 / 01889 日期1994年1月20日用于具有功率部件的多层混合电路的安装单元提供来自功率部件的改善的散热。 安装单元包括导热基板，其上安装有多层混合电路，该基板包括涂有铜膜的陶瓷板。

公开(公告)号：EP0862209A2

公开(公告)日：1998-09-02

申请号：EP98102845.9

申请日：1998-02-19

Applicant: Schulz-Harder, Jürgen, Dr.-Ing.

Inventor： Schulz-Harder, Jürgen, Dr.-Ing.

IPC: H01L23/373 ,  H01L21/48 ,  H05K3/40

CPC classification number: H05K3/0061 ,  C04B37/021 ,  C04B2237/366 ,  C04B2237/407 ,  C04B2237/62 ,  H01L21/4839 ,  H01L21/4867 ,  H01L23/3735 ,  H01L2924/0002 ,  H05K1/0306 ,  H05K3/0052 ,  H05K3/341 ,  H05K3/4061 ,  H05K3/4076 ,  H05K2201/0352 ,  H05K2201/0355 ,  H05K2201/0394 ,  H05K2201/0969 ,  H05K2201/09981 ,  H01L2924/00

Abstract: Die Erfindung bezieht sich auf ein neuartiges Verfahren zum Herstellen eines Keramik-Metall-Substrates für elektrische Schaltkreise, bei dem auf eine Keramikschicht beidseitig eine erste bzw. zweite Metallisierung aufgebracht wird, und zwar eine erste Metallisierung in Form einer Kupferfolie unter Verwendung des DCB-Verfahrens.

Abstract translation: 本发明涉及一种新颖的方法，用于制造用于电子电路的陶瓷 - 金属基片，在其上的第一或第二金属化的两侧的陶瓷层是通过使用DCB方法施加，即第一金属化在铜箔的形式 ，

公开(公告)号：EP0834917A1

公开(公告)日：1998-04-08

申请号：EP96115745.0

申请日：1996-10-01

Applicant: NITTO DENKO CORPORATION

Inventor： Naito, Toshiki, Nitto Denko Corp. ,  Ouchi, Kazuo, Nitto Denko Corp.

IPC: H01L23/31 ,  H01L23/498

CPC classification number: H01L24/81 ,  H01L23/4985 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81801 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H05K3/4007 ,  H05K3/423 ,  H05K2201/0347 ,  H05K2201/0355 ,  H05K2201/0367 ,  H05K2201/0394 ,  H05K2201/09481 ,  H05K2201/09563 ,  H05K2203/1572 ,  H01L2924/00

Abstract: Disclosed are a film carrier comprising an insulating layer (2') having laid therein an electrically conductive circuit such that the circuit is not exposed on the surface thereof, wherein conductive passages from the conductive circuit to one surface of the insulating layer (2') are formed in the insulating layer and via holes (3') from said conductive circuit to the other surface of the insulating layer (2') are formed and a semiconductor device prepared by mounting a semiconductor element (5) on the insulating layer (2') of the film carrier. The film carrier can sufficiently correspond to pitch-fining and high-density mounting of a semiconductor element wiring, can surely perform the connecting operation of inner lead bonding and outer lead bonding, and gives the mounting area of as small as possible.

Abstract translation: 公开了一种薄膜载体，其包括绝缘层（2'），其中放置有导电电路，使得该电路不在其表面上露出，其中从导电电路到绝缘层（2'）的一个表面的导电通路 形成在所述绝缘层中，并且形成从所述导电电路到绝缘层（2'）的另一个表面的通孔（3'）和通过将半导体元件（5）安装在绝缘层（2'）上而制备的半导体器件 '）的电影载体。 薄膜载体可以充分地对应于半导体元件布线的间距精细和高密度安装，可以可靠地执行内部引线接合和外部引线接合的连接操作，并且使安装面积尽可能小。

公开(公告)号：EP0491262B1

公开(公告)日：1997-11-05

申请号：EP91121132.4

申请日：1991-12-10

Applicant: Akyürek, Altan ,  Maier, Peter H. ,  Schulz-Harder, Jürgen, Dr.-Ing.

Inventor： Akyürek, Altan ,  Maier, Peter H. ,  Schulz-Harder, Jürgen, Dr.-Ing.

IPC: H01L25/07

CPC classification number: H05K1/0278 ,  H01L25/072 ,  H01L2224/48091 ,  H01L2924/01322 ,  H01L2924/1301 ,  H05K1/0306 ,  H05K3/0067 ,  H05K2201/0394 ,  H05K2201/0909 ,  H05K2203/302 ,  H01L2924/00014 ,  H01L2924/00

公开(公告)号：EP0793405A2

公开(公告)日：1997-09-03

申请号：EP97301300.6

申请日：1997-02-27

Applicant: CTS Corporation

Inventor： Ernsberger, Craig N. ,  Leach, Sarah E. ,  Allen Kathleen E. ,  Wenzel, Ralph J. ,  Meyer, Richard C.

IPC: H05K1/09 ,  H05K3/40 ,  H05K3/46

CPC classification number: H05K3/462 ,  H01B1/22 ,  H01L21/4857 ,  H01L23/49883 ,  H01L2924/0002 ,  H01L2924/09701 ,  H05K1/095 ,  H05K3/246 ,  H05K3/386 ,  H05K3/4069 ,  H05K3/4623 ,  H05K2201/0347 ,  H05K2201/0355 ,  H05K2201/0394 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/10378 ,  H05K2203/1131 ,  H05K2203/1453 ,  H05K2203/1461 ,  H01L2924/00

Abstract: Electronic assemblies comprising a sinterable composition are disclosed. The composition sinters reactively and/or non-reactively during the lamination cure cycle of the assembly. The composition generally comprises (i) at least one high melting particulate phase material, (ii) at least one low melting material, and (iii) an organic portion comprising a resin and a cross-linking agent.

Abstract translation: 电子组件包括烧结能够组成的游离缺失盘。 该组合物反应性烧结和/或所述组件的层压固化周期期间的非反应性。 所述组合物通常包含（i）至少一个高熔点颗粒相材料，（ⅱ）至少一种低熔点材料，和（iii）包含树脂和交联剂的有机部分。