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    Semiconductor device built-in substrate module and manufacturing method of the same
    44.
    发明专利
    Semiconductor device built-in substrate module and manufacturing method of the same 审中-公开
    半导体器件内置基板模块及其制造方法

    公开(公告)号：JP2013105992A

    公开(公告)日：2013-05-30

    申请号：JP2011250779

    申请日：2011-11-16

    申请人： Casio Comput Co Ltd ,  カシオ計算機株式会社

    发明人： WAKIZAKA SHINJI ,  AOKI YOSHITAKA

    IPC分类号： H05K3/46 ,  H01L23/12 ,  H05K1/16 ,  H05K3/00

    CPC分类号： H01L24/97 ,  H01L2223/6677 ,  H01L2224/12105 ,  H01L2224/19 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/3025 ,  H01L2224/82 ,  H01L2224/83 ,  H01L2924/00012

    摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device built-in substrate module which achieves high integration and downsizing of a semiconductor device including specific functions and simplifies and streamlines the manufacturing processes regarding component mounting, and to provide a manufacturing method of the semiconductor device built-in substrate module.SOLUTION: In a semiconductor device built-in substrate module 10, a substrate device part 20 where a semiconductor device 30 having a wafer level CSP structure is incorporated with a core substrate 21 and a coil part 50 serving as a function part having desired functions are integrally formed. Further, the substrate device part 20 and the coil part 50 are electrically connected with each other through wiring layers, vias, and through electrodes which form lamination wiring.

    摘要翻译： 解决的问题：提供一种半导体装置内置的基板模块，其实现了具有特定功能的半导体装置的高集成度和小型化，并简化并简化了关于部件安装的制造工艺，并提供了一种制造方法 半导体器件内置基板模块。 解决方案：在半导体器件内置衬底模块10中，将具有晶片级CSP结构的半导体器件30与芯基板21和作为功能部件的线圈部件50结合的衬底器件部件20 所需功能整体形成。 此外，基板器件部件20和线圈部件50通过布线层，通孔和形成层叠布线的通孔电极彼此电连接。 版权所有（C）2013，JPO＆INPIT

    Semiconductor package
    47.
    发明专利
    Semiconductor package 审中-公开
    半导体封装

    公开(公告)号：JP2013016842A

    公开(公告)日：2013-01-24

    申请号：JP2012197608

    申请日：2012-09-07

    申请人： Shinko Electric Ind Co Ltd ,  新光電気工業株式会社

    发明人： KUNIMOTO YUJI

    IPC分类号： H01L25/04 ,  H01L21/60 ,  H01L23/52 ,  H01L25/18

    CPC分类号： H01L2224/04105 ,  H01L2224/19 ,  H01L2224/24137 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2924/00012

    摘要： PROBLEM TO BE SOLVED: To provide a semiconductor package allowing increase in the density of a wiring pattern which can be led through a gap between exposed surfaces of bumps formed on respective electrode terminals in a plurality of semiconductor elements having different thicknesses and fixed to one surface of a support plate.SOLUTION: In the semiconductor package, a plurality of semiconductor elements 14a and 14b having different thicknesses are fixed to one surface of a support plate 10 through a resin layer 12 so that terminal surfaces of electrode terminals 16 of the semiconductor elements 14a and 14b may be flush. The resin layer 12 is provided on the entire of the one surface of the support plate 10. The semiconductor elements 14a and 14b have the opposite surfaces of the terminal surfaces fixed to the resin layer 12. There is provided an insulating layer 20 for covering at least a part of the terminal surfaces and lateral surfaces of the semiconductor elements 14a and 14b and the entire surface of the resin layer 12. Tapered bumps 18 formed on the terminal surfaces of the semiconductor elements 14a, 14b are formed penetrating through the insulating layer 20, and the tip surfaces of the tapered bumps 18 exposed on the surface of the insulating layer 20 are connected to wiring patterns 22.

    摘要翻译： 要解决的问题：提供一种半导体封装，其允许增加布线图案的密度，所述布线图案的密度可以通过在具有不同厚度的多个半导体元件中形成在各个电极端子上的凸块的暴露表面之间的间隙被引导，并且固定 到支撑板的一个表面。 解决方案：在半导体封装中，具有不同厚度的多个半导体元件14a和14b通过树脂层12固定在支撑板10的一个表面上，使得半导体元件14a的电极端子16和 14b可能是齐平的。 树脂层12设置在支撑板10的一个表面的整个表面上。半导体元件14a和14b具有固定在树脂层12上的端子表面的相对表面。设置有绝缘层20，用于覆盖在 半导体元件14a和14b的端面和侧表面的至少一部分以及树脂层12的整个表面。形成在半导体元件14a，14b的端子表面上的锥形凸起18形成为穿过绝缘层20 露出在绝缘层20的表面上的倾斜凸块18的端面与布线图案22连接。（C）2013，JPO＆INPIT