公开(公告)号：JP2012129261A

公开(公告)日：2012-07-05

申请号：JP2010277519

申请日：2010-12-13

申请人： Sumitomo Bakelite Co Ltd ,  住友ベークライト株式会社

发明人： NIKAIDO HIROMOTO ,  MAEDA MASAKATSU

IPC分类号： H01L23/12 ,  H01L25/10 ,  H01L25/11 ,  H01L25/18

CPC分类号： H01L21/568 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/96 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/15311

摘要： PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor element sealing body and a manufacturing method of a semiconductor package which simultaneously manufacture multiple packages, each of which includes a semiconductor element and secures electrical connection between an upper part and a lower part, and manufacture the packages with high reliability.SOLUTION: A manufacturing method of a semiconductor element sealing body of this invention is a method for manufacturing a semiconductor element sealing body 270 having semiconductor elements 26, conductor pillars 28, and a sealing part 27 sealing the semiconductor elements 26 and the conductor pillars 28. The manufacturing method includes: a placement process in which the semiconductor elements 26 are placed on a dummy substrate 101; a sealing part formation process in which the sealing part is formed so as to cover the dummy substrate 101 and the semiconductor elements 26; a conductor pillar formation process in which through holes 271 are formed in the sealing part 27, and then the conductive pillars 28 are formed in the through holes 271 to obtain the semiconductor element sealing body 270 on the dummy substrate 101; and a removal process in which the dummy substrate 101 is removed from the semiconductor element sealing body 270.

摘要翻译： 解决的问题：提供半导体元件密封体的制造方法和半导体封装的制造方法，其同时制造多个封装，每个封装包括半导体元件，并且确保上部和 较低的部件，并且制造具有高可靠性的包装。 解决方案：本发明的半导体元件密封体的制造方法是制造半导体元件密封体270的方法，半导体元件密封体270具有半导体元件26，导体柱28和密封半导体元件26和导体的密封部27 支柱28.制造方法包括：将半导体元件26放置在虚设基板101上的配置工序; 密封部形成工序，其中形成密封部以覆盖虚设基板101和半导体元件26; 在密封部分27中形成通孔271，然后在通孔271中形成导电柱28以在虚设基板101上获得半导体元件密封体270的导体柱形成工艺; 以及从半导体元件密封体270除去虚设基板101的去除处理。（C）2012，JPO＆INPIT

公开(公告)号：JP4927195B2

公开(公告)日：2012-05-09

申请号：JP2010109889

申请日：2010-05-12

申请人： ヘッドウェイテクノロジーズ インコーポレイテッド ,  新科實業有限公司SAE Magnetics(H.K.)Ltd.

发明人： 浩幸 伊藤 ,  芳高 佐々木 ,  寛 池島 ,  淳 飯島

IPC分类号： H01L25/065 ,  H01L25/07 ,  H01L25/10 ,  H01L25/11 ,  H01L25/18

CPC分类号： H01L24/96 ,  H01L21/6835 ,  H01L23/3171 ,  H01L24/06 ,  H01L24/16 ,  H01L24/25 ,  H01L24/29 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68359 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05553 ,  H01L2224/05647 ,  H01L2224/12105 ,  H01L2224/13099 ,  H01L2224/18 ,  H01L2224/32145 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2225/06513 ,  H01L2225/06551 ,  H01L2225/1035 ,  H01L2225/1064 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/078 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/18162 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/00

摘要： A composite layered chip package includes a plurality of subpackages stacked. Each subpackage includes a main body, and wiring disposed on a side surface of the main body. The main body has a main part that includes at least one first-type layer portion. For any two vertically adjacent subpackages, the main body of the lower subpackage has a plurality of first terminals that are arranged on the top surface of the main part, while the main body of the upper subpackage has a plurality of second terminals that are arranged on the bottom surface of the main part. The main part of the main body of at least one of the plurality of subpackages includes at least one second-type layer portion. The first-type layer portion includes a conforming semiconductor chip, while the second-type layer portion includes a defective semiconductor chip.

公开(公告)号：JP2011524647A

公开(公告)日：2011-09-01

申请号：JP2011514614

申请日：2009-06-15

申请人： テセラ・リサーチ・リミテッド・ライアビリティ・カンパニー

发明人： クライマン，モシェ ,  ハーバ，ベルガセム ,  ミルカリミ，ローラ ,  モハメッド，イリヤス

IPC分类号： H01L25/065 ,  H01L23/12 ,  H01L25/07 ,  H01L25/18

CPC分类号： H01L25/105 ,  H01L23/3114 ,  H01L25/50 ,  H01L2224/24145 ,  H01L2225/06551 ,  H01L2225/1035 ,  H01L2225/1064 ,  H01L2924/01067 ,  H01L2924/01322 ,  Y10T29/49144

摘要： 超小形電子組立体（３００）は、第１の超小形電子装置（２００）と、第２の超小形電子装置（２００）とを含む。 第１の超小形電子装置（２００）と第２の超小形電子装置（２００）との各々は、少なくとも１つの半導体ダイ（１０４）を含むダイ構造体を有し、第１の表面（２０１）と、第１の表面（２０１）から遠くに位置する第２の表面（２０３）と、第１の表面（２０１）及び第２の表面（２０３）から遠ざかって直角以外の角度で延びる少なくとも１つの縁部表面（１３４）とを有する。 （部分１１０、１２４、１２２、１２６を含みうる）少なくとも１つの導電要素が、第１の表面に沿って延びて、第１の超小形電子装置（２００）の少なくとも１つの縁部表面（１３４）と第２の超小形電子装置（２００）の少なくとも１つの縁部表面（１３４）とのうちの少なくとも１つに達しかつ第２の表面（２０３）に達する。 第１の超小形電子装置（２００）の少なくとも１つの導電素子は、前記第２の超小形電子装置（２００）に導電的に結合され、これにより導電路が第１の超小形電子装置（２００）と第２の超小形電子装置（２００）との間に形成される。

公开(公告)号：JP2011165741A

公开(公告)日：2011-08-25

申请号：JP2010024097

申请日：2010-02-05

申请人： Renesas Electronics Corp ,  ルネサスエレクトロニクス株式会社

发明人： GOTO MASAKATSU ,  ENOMOTO MINORU

IPC分类号： H01L23/12

CPC分类号： H01L24/81 ,  H01L23/3121 ,  H01L23/49816 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/73 ,  H01L25/105 ,  H01L25/16 ,  H01L2224/16225 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81191 ,  H01L2224/83192 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/01046 ,  H01L2924/01051 ,  H01L2924/01064 ,  H01L2924/01075 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/3025 ,  H01L2924/00012 ,  H01L2924/00

摘要： PROBLEM TO BE SOLVED: To provide technique for making a multilayer wiring board thin for a semiconductor device having the multilayer wiring board in which a semiconductor chip is embedded. SOLUTION: The semiconductor device having a bump electrode BMP formed on a principal surface (element formation surface) of the semiconductor chip CHP embedded in the chip-embedded wiring board EMPAC1 is characterized in that an insulating film DAF is formed on a reverse surface (a surface on the opposite side from the principal surface) of the semiconductor chip CHP. Consequently, it is not necessary to form a prepreg PG on the reverse surface of the semiconductor chip CHP, so the effect of reducing the thickness of the chip-embedded wiring board EMPAC1 in which the semiconductor chip CHP is embedded is obtained. COPYRIGHT: (C)2011,JPO&INPIT

摘要翻译： 要解决的问题：提供一种薄膜化用于具有嵌入了半导体芯片的多层布线基板的半导体器件的多层布线基板的技术。 解决方案：具有形成在嵌入在芯片嵌入式布线板EMPAC1中的半导体芯片CHP的主表面（元件形成表面）上的突起电极BMP的半导体器件的特征在于，绝缘膜DAF形成在反向 表面（与主表面相反一侧的表面）。 因此，不需要在半导体芯片CHP的背面上形成预浸料PG，所以可以获得降低嵌入有半导体芯片CHP的芯片嵌入布线基板EMPAC1的厚度的效果。 版权所有（C）2011，JPO＆INPIT

公开(公告)号：JP4752825B2

公开(公告)日：2011-08-17

申请号：JP2007217876

申请日：2007-08-24

申请人： カシオ計算機株式会社

发明人： 裕康 定別当

IPC分类号： H01L23/12

CPC分类号： H01L23/5389 ,  H01L21/6835 ,  H01L23/3675 ,  H01L25/105 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/24195 ,  H01L2224/24227 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/82039 ,  H01L2224/83192 ,  H01L2224/92144 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1094 ,  H01L2924/01015 ,  H01L2924/01078 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/3025 ,  H01L2924/3511 ,  H01L2924/00

摘要： A semiconductor device includes a semiconductor constituent having a semiconductor substrate and a plurality of electrodes for external connection provided under the semiconductor substrate. An under-layer insulating film is provided under and around the semiconductor constituent. A plurality of under-layer wires are provided under the under-layer insulating film and electrically connected to the electrodes for external connection of the semiconductor constituent. An insulating layer is provided around the semiconductor constituent and on the under-layer insulating film. A frame-like insulating substrate is embedded in an upper surface of the insulating layer and positioned around the semiconductor constituent. A plurality of upper-layer wires are provided on the insulating substrate. A base plate on which the semiconductor constituent and the insulating layer are mounted is removed.

公开(公告)号：JP4589170B2

公开(公告)日：2010-12-01

申请号：JP2005132539

申请日：2005-04-28

申请人： 新光電気工業株式会社

发明人： 明宜 井上 ,  篤典 加治木 ,  広幸 加藤 ,  智樹 小林 ,  紀治 島田 ,  浩 清水

IPC分类号： H05K9/00 ,  H05K1/02 ,  H05K3/28

CPC分类号： H01L25/0655 ,  H01L21/561 ,  H01L23/295 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/24 ,  H01L24/48 ,  H01L24/82 ,  H01L24/97 ,  H01L25/105 ,  H01L2223/6677 ,  H01L2224/16225 ,  H01L2224/24226 ,  H01L2224/48227 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2224/97 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/1531 ,  H01L2924/1533 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/3025 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2224/0401 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A resin layer in which adhesion to a conductive film is higher than that of a sealing resin to the conductive film is disposed on the sealing resin in which it is difficult to form the conductive film, and wiring patterns electrically connected to electronic components are disposed on the resin layer.

公开(公告)号：JP2010245107A

公开(公告)日：2010-10-28

申请号：JP2009089223

申请日：2009-04-01

申请人： Shinko Electric Ind Co Ltd ,  新光電気工業株式会社

发明人： KATAGIRI FUMIMASA

IPC分类号： H01L23/12 ,  H01L25/065 ,  H01L25/07 ,  H01L25/18

CPC分类号： H01L21/568 ,  H01L23/3121 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/48 ,  H01L24/82 ,  H01L25/03 ,  H01L25/105 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/24247 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： PROBLEM TO BE SOLVED: To provide a semiconductor mounting substrate that has a conductive part that electrically conducts a substrate in a thickness direction, and that can be easily applied to usage such as forming a composite substrate by laminating the substrates, and to provide a method of manufacturing the same.
SOLUTION: A semiconductor apparatus has a substrate 16 having a semiconductor element 12, and a resin molding part 14 integrally provided while having a surface of the semiconductor element 12, on which an electrode terminal 13 of the semiconductor element 12 is formed, in common with a surface direction, and a wiring layer 30 formed on one surface of the substrate 16 on which the electrode terminal 13 is formed. A plurality of conductive parts 18 that penetrate the resin molding part 14 in the thickness direction and electrically conducts to the wiring layer 30, is provided in the resin molding part 14.
COPYRIGHT: (C)2011,JPO&INPIT

摘要翻译： 解决的问题：提供一种半导体安装基板，其具有在厚度方向上导电的基板的导电部，并且可以容易地应用于诸如通过层叠基板而形成复合基板的用途，并且 提供其制造方法。 解决方案：半导体装置具有半导体元件12的基板16和半导体元件12的表面一体形成的树脂成型部14，半导体元件12的电极端子13形成在半导体元件12的表面上， 与表面方向相同，以及形成在其上形成有电极端子13的基板16的一个表面上的布线层30。 在树脂成型部14中设置有多个在厚度方向上贯通树脂成型部14并与布线层30导通的导电部18.权利要求（C）2011，JPO＆INPIT

公开(公告)号：JP2010232333A

公开(公告)日：2010-10-14

申请号：JP2009077033

申请日：2009-03-26

申请人： Shinko Electric Ind Co Ltd ,  新光電気工業株式会社

发明人： OI ATSUSHI

IPC分类号： H01L23/12

CPC分类号： H01L23/49827 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/19 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/82 ,  H01L25/105 ,  H01L2221/68345 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05147 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48647 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/82001 ,  H01L2224/85447 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device capable of being downsized in the thickness direction thereof, to provide a method of manufacturing the semiconductor device, and to provide an electronic device. SOLUTION: The semiconductor device includes: a multilayer wiring structure 31 having a through part 35; and a through electrode 33 provided in the multilayer wiring structure 31 and having first and second connection faces 41A and 42A exposed from faces 31A and 31B of the multilayer wiring structure 31. An electronic component 22 is housed in the through part 35 so as not to project from the first and second connection faces 41A and 42A, and the electronic component 22 and the through electrode 33 are electrically connected through a wiring pattern 25 directly connected to an electrode pad 45 of the electronic component 22 and the first connection face 41A of the through electrode. COPYRIGHT: (C)2011,JPO&INPIT

摘要翻译： 解决的问题：提供能够在其厚度方向上减小尺寸的半导体器件，以提供半导体器件的制造方法，并提供电子器件。 解决方案：半导体器件包括：具有通孔部分35的多层布线结构31; 以及设置在多层布线结构31中并且具有从多层布线结构31的面31A和31B露出的第一和第二连接面41A和42A的贯通电极33.电子部件22容纳在贯通部35中， 从第一和第二连接面41A和42A突出并且电子部件22和贯通电极33通过直接连接到电子部件22的电极焊盘45的布线图案25和第二连接面41A电连接 通过电极。 版权所有（C）2011，JPO＆INPIT

公开(公告)号：JP2010219451A

公开(公告)日：2010-09-30

申请号：JP2009067097

申请日：2009-03-18

申请人： Sumitomo Bakelite Co Ltd ,  住友ベークライト株式会社

发明人： NIKAIDO HIROMOTO ,  MEURA TORU

IPC分类号： H01L25/065 ,  H01L23/12 ,  H01L25/07 ,  H01L25/18

CPC分类号： H01L24/96 ,  H01L21/568 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/19 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/00 ,  H01L2924/00012

摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor element sealing body and a method of manufacturing a semiconductor package such that packages including semiconductor elements can be manufactured in a lump with superior productivity, and the packages can be manufactured with high reliability. SOLUTION: The invention relates to the method of manufacturing the semiconductor element sealing body 270 having a sheet material 25' having through-holes 251 formed, a sheet material 29' having conductor columns 28 and a filling portion 291, a semiconductor element 26 having electrode pads, and the sealing portion 27 for sealing the semiconductor element 26, the method of manufacturing the semiconductor element sealing body including the steps of: preparing a laminate 200 of the sheet material 25' and sheet material 29'; forming the through-holes 251 in a thickness direction of the sheet material 25'; disposing the semiconductor element 26 on the sheet material 25' so that the electrode pads may correspond to the through-holes 251; and forming the sealing portion 27 by sealing the inside of the filling portion 291 where the semiconductor elements 26 are arranged in a state wherein the sheet material 25' and semiconductor elements 26 are covered. COPYRIGHT: (C)2010,JPO&INPIT

摘要翻译： 要解决的问题：提供一种制造半导体元件密封体的方法和制造半导体封装的方法，使得可以以优异的生产率一体地制造包括半导体元件的封装，并且封装可以用 高可靠性。 解决方案：本发明涉及制造具有形成有通孔251的片材25'，具有导体柱28的片材29'和填充部291的半导体元件密封体270的制造方法，半导体元件 具有电极焊盘的密封部分27和用于密封半导体元件26的密封部分27，制造半导体元件密封体的方法包括以下步骤：制备片材25'和片材29'的层压体200; 在片材25'的厚度方向上形成通孔251; 将半导体元件26设置在片材25'上，使得电极焊盘可以对应于通孔251; 并且通过在片状材料25'和半导体元件26被覆盖的状态下密封半导体元件26布置的填充部分291的内部而形成密封部分27。 版权所有（C）2010，JPO＆INPIT

公开(公告)号：JP4550102B2

公开(公告)日：2010-09-22

申请号：JP2007277308

申请日：2007-10-25

申请人： スパンション エルエルシー

发明人： 有紀 小出 ,  弘一 目黒

IPC分类号： H01L23/12 ,  H01L25/065 ,  H01L25/07 ,  H01L25/10 ,  H01L25/11 ,  H01L25/18

CPC分类号： H01L21/568 ,  H01L21/561 ,  H01L23/3107 ,  H01L24/45 ,  H01L24/48 ,  H01L25/105 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/45144 ,  H01L2224/48095 ,  H01L2224/48471 ,  H01L2224/48479 ,  H01L2224/73265 ,  H01L2224/85001 ,  H01L2224/854 ,  H01L2224/85951 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06575 ,  H01L2225/06596 ,  H01L2225/1035 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10161 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18165 ,  H01L2924/19107 ,  H01L2924/351 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/4554

摘要： A semiconductor package having a molding unit that seals bonding wires connected to electrode pads of a semiconductor chip is provided with through electrode units comprising bonding wires embedded therein and penetrating the molding unit. A leading end of the respective through electrode units is exposed from an upper surface of the molding unit and a lower surface of the molding unit.