Printed circuit board, and its manufacturing method
    81.
    发明专利
    Printed circuit board, and its manufacturing method 审中-公开
    印刷电路板及其制造方法

    公开(公告)号:JP2008016630A

    公开(公告)日:2008-01-24

    申请号:JP2006186152

    申请日:2006-07-06

    Inventor: NAKANO TAKAHIRO

    Abstract: PROBLEM TO BE SOLVED: To provide a printed circuit board which is capable of preventing a surface insulating resin layer from being warped at reflow in the mounting region of a semiconductor device.
    SOLUTION: Conductor wiring layers 12, and 14b and interlayer insulating resin layers 13 are alternately laminated on both the main surfaces of a core board 11, and a surface insulating resin layer 16 is formed covering the uppermost conductor wiring layer formed on the surface of the core board 11 for the formation of a multilayer printed circuit board 1. A square region is removed from the surface insulating resin layer 16 which is formed on the interlayer insulating resin layer 13, to form a vacant area 17 at the center within the mounting region 10 of a semiconductor device in a region just under the semiconductor device excluding conductor lands 14a bonded to the external electrodes of the semiconductor device.
    COPYRIGHT: (C)2008,JPO&INPIT

    Abstract translation: 要解决的问题:提供一种能够防止在半导体器件的安装区域中的表面绝缘树脂层在回流时翘曲的印刷电路板。 解决方案:导体布线层12和14b以及层间绝缘树脂层13交替层叠在芯板11的两个主表面上,并且形成表面绝缘树脂层16,覆盖形成在芯板11上的最上层的导体布线层 用于形成多层印刷电路板1的芯板11的表面。从形成在层间绝缘树脂层13上的表面绝缘树脂层16去除正方形区域,以在中心内形成空区域17 在半导体器件正下方的区域中的半导体器件的安装区域10,除了接合到半导体器件的外部电极的导体焊盘14a之外。 版权所有(C)2008,JPO&INPIT

    Thin film embedded capacitance and its manufacturing method, and printed wiring board
    85.
    发明专利
    Thin film embedded capacitance and its manufacturing method, and printed wiring board 有权
    薄膜嵌入电容及其制造方法和印刷线路板

    公开(公告)号:JP2007042989A

    公开(公告)日:2007-02-15

    申请号:JP2005227798

    申请日:2005-08-05

    Inventor: TSUKADA KIYOTAKA

    Abstract: PROBLEM TO BE SOLVED: To provide a thin film embedded capacitance having a large electric capacitance per unit, and to provide its manufacturing method. SOLUTION: The thin film embedded capacitance comprises a metal thin film 2P for wiring comprising a metal material in an unyielded state; a first electrode 4 formed on the metal thin film for wiring; a dielectric material layer 6 formed by a sputtering method on the first electrode and the metal thin film for wiring at a temperature not lower than room temperature, and at lower than the yielding temperature of the metal thin film for wiring, and having a smaller coefficient of thermal expansion than that of the metal thin film wiring; and a second electrode 8 formed on the dielectric material layer. Its manufacturing method is also provided. COPYRIGHT: (C)2007,JPO&INPIT

    Abstract translation: 要解决的问题:提供每单位具有大电容量的薄膜嵌入式电容器,并提供其制造方法。 解决方案:薄膜嵌入电容包括用于布线的金属薄膜2P,其包括处于非屏蔽状态的金属材料; 形成在用于布线的金属薄膜上的第一电极4; 通过溅射法在第一电极上形成的电介质层6和用于布线的金属薄膜,其温度不低于室温,低于布线金属薄膜的屈服温度,并且具有较小的系数 的热膨胀比金属薄膜布线; 以及形成在电介质材料层上的第二电极8。 还提供其制造方法。 版权所有(C)2007,JPO&INPIT

    Substrate for semiconductor device
    88.
    发明专利

    公开(公告)号:JP2004327814A

    公开(公告)日:2004-11-18

    申请号:JP2003122058

    申请日:2003-04-25

    Abstract: PROBLEM TO BE SOLVED: To provide a substrate for semiconductor device that can mount a semiconductor element with a reduced strength by preventing cracks generating in a substrate in the case when a material approximating to the coefficient of thermal expansion of the semiconductor element is used as a core substrate.
    SOLUTION: The substrate for semiconductor device is provided with wiring patterns 12, 14 and 16 formed on one surface or both surfaces of a core substrate 10 with resin layers 18, 20 and 22 in between. The core substrate 10 is made of a material approximating to the coefficient of thermal expansion of the semiconductor element, and a resin layer 24 as the outermost layer of the substrate is made of a resin material of which strength and elongation is higher than that of one used for the resin layers 18, 20 and 22 inside the substrate. Thus, a failure such as cracks or deformation occurring in the substrate due to a thermal stress between the core substrate 10 and the resin layers 18, 20 and 22 and the wiring patterns 12, 14 and 16 inside the substrate can be prevented.
    COPYRIGHT: (C)2005,JPO&NCIPI

    Laminated film and film carrier tape for packaging electronic component
    90.
    发明专利
    Laminated film and film carrier tape for packaging electronic component 审中-公开
    用于包装电子元件的层压膜和胶片胶带

    公开(公告)号:JP2003059979A

    公开(公告)日:2003-02-28

    申请号:JP2001249499

    申请日:2001-08-20

    Abstract: PROBLEM TO BE SOLVED: To provide a laminated film for packaging electronic components that can easily and effectively reduce the warpage in a widthwise direction of the laminated firm for packaging electronic components, and to provide a film carrier tape for packaging electronic components.
    SOLUTION: In a laminated film 10 where a conductor layer 11 and an insulating film 14 are subjected to thermocompression bonding, a coefficient of thermal expansion in the widthwise direction of the insulating film 14 is nearly the same as or larger than that in the widthwise direction of the conductor layer 11.
    COPYRIGHT: (C)2003,JPO

    Abstract translation: 要解决的问题:提供一种用于包装电子部件的层压膜,其可以容易且有效地减少用于包装电子部件的层压制品的宽度方向的翘曲,并且提供用于包装电子部件的胶片载带。 解决方案:在导体层11和绝缘膜14进行热压接的层叠膜10中,绝缘膜14的宽度方向的热膨胀系数几乎与宽度方向的热膨胀系数相同或者更大 的导体层11。

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