公开(公告)号：US20050233569A1

公开(公告)日：2005-10-20

申请号：US11091869

申请日：2005-03-29

Applicant: Yonghwan Kwon ,  Chungsun Lee ,  Sayoon Kang

Inventor： Yonghwan Kwon ,  Chungsun Lee ,  Sayoon Kang

IPC: G02F1/1345 ,  H01L21/44 ,  H01L21/60 ,  H01L23/485 ,  H01L23/50

CPC classification number: H01L24/11 ,  H01L24/02 ,  H01L24/13 ,  H01L2224/02331 ,  H01L2224/0235 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/1319 ,  H01L2224/136 ,  H01L2924/0001 ,  H01L2924/01005 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00014

Abstract: A semiconductor device employing the bump structure includes a plurality of bump structures arrayed along a substrate in a first direction. Each bump structure has a width in the first direction greater than a pitch gap between successively arrayed bump structures, and at least one bump structure has a sidewall facing in the first direction that is non-conductive.

Abstract translation: 采用该凸块结构的半导体器件包括在第一方向上沿衬底排列的多个凸块结构。 每个凸块结构在第一方向上的宽度大于连续排列的凸起结构之间的间距间隙，并且至少一个凸块结构具有面向不导通的第一方向的侧壁。

公开(公告)号：US09059072B2

公开(公告)日：2015-06-16

申请号：US14294052

申请日：2014-06-02

Applicant: Eun-Kyoung Choi ,  SeYoung Jeong ,  Kwang-chul Choi ,  Tae Hong Min ,  Chungsun Lee ,  Jung-Hwan Kim

Inventor： Eun-Kyoung Choi ,  SeYoung Jeong ,  Kwang-chul Choi ,  Tae Hong Min ,  Chungsun Lee ,  Jung-Hwan Kim

IPC: H01L23/02 ,  H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H01L25/065 ,  H01L25/00 ,  H01L23/367 ,  H01L21/683 ,  H01L23/36 ,  H01L23/522 ,  H01L25/18

CPC classification number: H01L24/97 ,  H01L21/561 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/36 ,  H01L23/3672 ,  H01L23/3677 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2224/73253 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/06506 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01068 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Provided are a semiconductor package and a method of fabricating the same. In one embodiment, to fabricate a semiconductor package, a wafer having semiconductor chips fabricated therein is provided. A heat sink layer is formed over the wafer. The heat sink layer contacts top surfaces of the semiconductor chips. Thereafter, the plurality of semiconductor chips are singulated from the wafer.

Abstract translation: 提供半导体封装及其制造方法。 在一个实施例中，为了制造半导体封装，提供其中制造有半导体芯片的晶片。 在晶片上形成散热层。 散热层接触半导体芯片的顶表面。 此后，从晶片上分离多个半导体芯片。

公开(公告)号：US20120329249A1

公开(公告)日：2012-12-27

申请号：US13530543

申请日：2012-06-22

Applicant: Jung-Seok Ahn ,  II Hwan Kim ,  Jung-Hwan Kim ,  Sangwook Park ,  Chungsun Lee ,  Kwang-chul Choi

Inventor： Jung-Seok Ahn ,  II Hwan Kim ,  Jung-Hwan Kim ,  Sangwook Park ,  Chungsun Lee ,  Kwang-chul Choi

IPC: H01L21/78

CPC classification number: H01L21/78 ,  H01L21/561 ,  H01L21/563 ,  H01L21/6835 ,  H01L21/6836 ,  H01L23/3128 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/81 ,  H01L24/83 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/68336 ,  H01L2221/6834 ,  H01L2221/68368 ,  H01L2221/68381 ,  H01L2224/13025 ,  H01L2224/13101 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: Methods of manufacturing a plurality of semiconductor chips are provided. The method may include providing a middle layer between a substrate and a carrier to combine the carrier with the substrate, thinning the substrate; after thinning the substrate, separating the carrier from the substrate; and after the carrier is separated from the substrate, cutting the substrate to form the plurality of semiconductor chips, wherein the middle layer is adhered to the carrier with a first bonding force, and the middle layer is adhered to the substrate with a second bonding force, and wherein the second bonding force is greater than the first bonding force.

Abstract translation: 提供制造多个半导体芯片的方法。 该方法可以包括在衬底和载体之间提供中间层以将载体与衬底组合，使衬底变薄; 在使衬底变薄之后，将衬底与衬底分离; 在载体与基板分离之后，切割基板以形成多个半导体芯片，其中中间层以第一结合力粘附到载体上，并且中间层以第二结合力粘附到基板 并且其中所述第二结合力大于所述第一结合力。

公开(公告)号：US20170004990A1

公开(公告)日：2017-01-05

申请号：US15112429

申请日：2014-03-19

Applicant: Un-Byoung Kang ,  Joonsik Sohn ,  Jung-Seok Ahn ,  Chungsun Lee ,  Taeje Cho

Inventor： Un-Byoung Kang ,  Joonsik Sohn ,  Jung-Seok Ahn ,  Chungsun Lee ,  Taeje Cho

IPC: H01L21/683 ,  H01L23/00 ,  H01L25/00 ,  H01L21/78 ,  H01L23/544 ,  H01L25/065 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L21/6836 ,  H01L21/48 ,  H01L21/4853 ,  H01L21/56 ,  H01L21/561 ,  H01L21/563 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/544 ,  H01L24/02 ,  H01L24/03 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381 ,  H01L2223/5446 ,  H01L2224/0239 ,  H01L2224/03002 ,  H01L2224/06181 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13147 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/92 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2225/06582 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/11 ,  H01L21/304 ,  H01L2221/68363 ,  H01L2224/81005 ,  H01L2224/83005 ,  H01L2224/03 ,  H01L2224/85

Abstract: Provided are methods of fabricating a semiconductor device. According to the method, a first glue layer, a first release layer, a second glue layer, and a second release layer may be sequentially interposed between a carrier and a device wafer. All of the first glue layer, the first release layer, the second glue layer, and the second release layer may be formed of thermosetting resin.

Abstract translation: 提供制造半导体器件的方法。 根据该方法，第一胶合层，第一剥离层，第二胶层和第二剥离层可以顺序插入载体和器件晶片之间。 所有第一胶合层，第一释放层，第二胶层和第二剥离层可以由热固性树脂形成。

公开(公告)号：US20120211885A1

公开(公告)日：2012-08-23

申请号：US13188554

申请日：2011-07-22

Applicant: YunSeok Choi ,  ChungSun Lee

Inventor： YunSeok Choi ,  ChungSun Lee

IPC: H01L23/498

CPC classification number: H01L21/563 ,  H01L21/486 ,  H01L23/147 ,  H01L23/3128 ,  H01L23/49827 ,  H01L25/105 ,  H01L2221/68331 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81815 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/18161 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A semiconductor package having a reduced size by including an interposer having through substrate vias (TSVs), the semiconductor package may comprise a lower semiconductor package which includes a lower base substrate, an interposer with TSVs on the lower base substrate, and a lower semiconductor chip on the interposer and electrically connected to the interposer. The semiconductor package may include an upper semiconductor package on the lower semiconductor package including an upper semiconductor chip and package connecting members on the interposer and electrically connect the upper semiconductor package to the interposer. An exterior molding member may be provided.

Abstract translation: 通过包括具有通过衬底通孔（TSV）的插入件的尺寸减小的半导体封装，半导体封装可以包括下半导体封装，其包括下基底衬底，在下基底衬底上具有TSV的插入件和下半导体芯片 并且与内插器电连接。 半导体封装可以包括在下半导体封装上的上半导体封装，包括上半导体芯片和封装在内插器上的连接构件，并将上半导体封装电连接到插入器。 可以设置外部成型构件。

公开(公告)号：US20120091580A1

公开(公告)日：2012-04-19

申请号：US13211574

申请日：2011-08-17

Applicant: SeYoung Jeong ,  Hogeon Song ,  Chungsun Lee ,  Ho-Jin Lee

Inventor： SeYoung Jeong ,  Hogeon Song ,  Chungsun Lee ,  Ho-Jin Lee

IPC: H01L23/48

CPC classification number: H01L23/481 ,  H01L21/563 ,  H01L21/76898 ,  H01L23/3128 ,  H01L24/04 ,  H01L24/05 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/48 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2221/68372 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/0557 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/13009 ,  H01L2224/13025 ,  H01L2224/1403 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2224/73257 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06544 ,  H01L2225/06562 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/1304 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19104 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Provided is a semiconductor device. The semiconductor device may include a first semiconductor chip that includes a first through silicon via having a first protrusion height and a second through silicon via having a second protrusion height greater than the first protrusion height which are penetrating at least a portion of the first semiconductor chip, a second semiconductor chip may be electrically connected to the first through silicon via, and a third semiconductor chip may be electrically connected to the second through silicon via.

Abstract translation: 提供一种半导体器件。 半导体器件可以包括第一半导体芯片，其包括具有第一突起高度的第一至第二硅通孔以及具有大于第一突出高度的第二突出高度的第二穿透硅通孔，该第二突出高度穿过第一半导体芯片的至少一部分 ，第二半导体芯片可以电连接到第一通孔硅通孔，并且第三半导体芯片可以电连接到第二通孔硅通孔。

公开(公告)号：US20090305494A1

公开(公告)日：2009-12-10

申请号：US12461459

申请日：2009-08-12

Applicant: Yonghwan Kwon ,  Chungsun Lee ,  Sayoon Kang

Inventor： Yonghwan Kwon ,  Chungsun Lee ,  Sayoon Kang

IPC: H01L21/768

CPC classification number: H01L24/11 ,  H01L24/02 ,  H01L24/13 ,  H01L2224/02331 ,  H01L2224/0235 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/1319 ,  H01L2224/136 ,  H01L2924/0001 ,  H01L2924/01005 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00014

Abstract: A semiconductor device employing the bump structure includes a plurality of bump structures arrayed along a substrate in a first direction. Each bump structure has a width in the first direction greater than a pitch gap between successively arrayed bump structures, and at least one bump structure has a sidewall facing in the first direction that is non-conductive.

Abstract translation: 采用该凸块结构的半导体器件包括在第一方向上沿衬底排列的多个凸块结构。 每个凸块结构在第一方向上的宽度大于连续排列的凸起结构之间的间距间隙，并且至少一个凸块结构具有面向不导通的第一方向的侧壁。

公开(公告)号：US08933561B2

公开(公告)日：2015-01-13

申请号：US13211574

申请日：2011-08-17

Applicant: SeYoung Jeong ,  Hogeon Song ,  Chungsun Lee ,  Ho-Jin Lee

Inventor： SeYoung Jeong ,  Hogeon Song ,  Chungsun Lee ,  Ho-Jin Lee

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L23/481 ,  H01L21/563 ,  H01L21/76898 ,  H01L23/3128 ,  H01L24/04 ,  H01L24/05 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/48 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2221/68372 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/0557 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/13009 ,  H01L2224/13025 ,  H01L2224/1403 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2224/73257 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06544 ,  H01L2225/06562 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/1304 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19104 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Provided is a semiconductor device. The semiconductor device may include a first semiconductor chip that includes a first through silicon via having a first protrusion height and a second through silicon via having a second protrusion height greater than the first protrusion height which are penetrating at least a portion of the first semiconductor chip, a second semiconductor chip may be electrically connected to the first through silicon via, and a third semiconductor chip may be electrically connected to the second through silicon via.

Abstract translation: 提供一种半导体器件。 半导体器件可以包括第一半导体芯片，其包括具有第一突起高度的第一至第二硅通孔以及具有大于第一突出高度的第二突出高度的第二穿透硅通孔，该第二突出高度穿过第一半导体芯片的至少一部分 ，第二半导体芯片可以电连接到第一通孔硅通孔，并且第三半导体芯片可以电连接到第二通孔硅通孔。

公开(公告)号：US08928132B2

公开(公告)日：2015-01-06

申请号：US13188554

申请日：2011-07-22

Applicant: YunSeok Choi ,  ChungSun Lee

Inventor： YunSeok Choi ,  ChungSun Lee

IPC: H01L23/02 ,  H01L21/56 ,  H01L23/31 ,  H01L25/10 ,  H01L23/14 ,  H01L23/498 ,  H01L21/48

CPC classification number: H01L21/563 ,  H01L21/486 ,  H01L23/147 ,  H01L23/3128 ,  H01L23/49827 ,  H01L25/105 ,  H01L2221/68331 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81815 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/18161 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A semiconductor package having a reduced size by including an interposer having through substrate vias (TSVs), the semiconductor package may comprise a lower semiconductor package which includes a lower base substrate, an interposer with TSVs on the lower base substrate, and a lower semiconductor chip on the interposer and electrically connected to the interposer. The semiconductor package may include an upper semiconductor package on the lower semiconductor package including an upper semiconductor chip and package connecting members on the interposer and electrically connect the upper semiconductor package to the interposer. An exterior molding member may be provided.

Abstract translation: 通过包括具有通过衬底通孔（TSV）的插入件的尺寸减小的半导体封装，半导体封装可以包括下半导体封装，其包括下基底衬底，在下基底衬底上具有TSV的插入件和下半导体芯片 并且与内插器电连接。 半导体封装可以包括在下半导体封装上的上半导体封装，包括上半导体芯片和封装在内插器上的连接构件，并将上半导体封装电连接到插入器。 可以设置外部成型构件。

公开(公告)号：US20140300004A1

公开(公告)日：2014-10-09

申请号：US14294052

申请日：2014-06-02

Applicant: Eun-Kyoung CHOI ,  SeYoung JEONG ,  Kwang-chul CHOI ,  Tae Hong MIN ,  Chungsun LEE ,  Jung-Hwan KIM

Inventor： Eun-Kyoung CHOI ,  SeYoung JEONG ,  Kwang-chul CHOI ,  Tae Hong MIN ,  Chungsun LEE ,  Jung-Hwan KIM

IPC: H01L23/00 ,  H01L23/367 ,  H01L23/522

CPC classification number: H01L24/97 ,  H01L21/561 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/36 ,  H01L23/3672 ,  H01L23/3677 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2224/73253 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/06506 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01068 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Provided are a semiconductor package and a method of fabricating the same. In one embodiment, to fabricate a semiconductor package, a wafer having semiconductor chips fabricated therein is provided. A heat sink layer is formed over the wafer. The heat sink layer contacts top surfaces of the semiconductor chips. Thereafter, the plurality of semiconductor chips are singulated from the wafer.

Abstract translation: 提供半导体封装及其制造方法。 在一个实施例中，为了制造半导体封装，提供其中制造有半导体芯片的晶片。 在晶片上形成散热层。 散热层接触半导体芯片的顶表面。 此后，从晶片上分离多个半导体芯片。