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    METHOD OF APPLICATION OF A CARRIER TO A DEVICE WAFER
    1.
    发明申请
    METHOD OF APPLICATION OF A CARRIER TO A DEVICE WAFER 审中-公开
    将载体应用于器件滤波器的方法

    公开(公告)号：US20150340264A1

    公开(公告)日：2015-11-26

    申请号：US14759400

    申请日：2014-01-08

    Applicant: AMS AG

    Inventor： Joerg SIEGERT ,  Martin SCHREMS ,  Jochen KRAFT ,  Franz SCHRANK

    IPC: H01L21/683 ,  H01L21/768

    CPC classification number: H01L21/6836 ,  H01L21/6835 ,  H01L21/76898 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381 ,  Y10T156/10

    Abstract: A device wafer having a main surface including an edge region and a carrier having a further main surface including an annular surface region corresponding to the edge region of the device wafer are provided. An adhesive is applied in the edge region and/or in the annular surface region, but not on the remaining areas of the main surfaces. The device wafer is fastened to the carrier by the adhesive. The main surface and the further main surface are brought into contact with one another when the device wafer is fastened to the carrier, while the main surface and the further main surface are fastened to one another only in the edge region. The device wafer is removed from the carrier after further process steps, which may include the formation of through-wafer vias in the device wafer.

    Abstract translation: 提供了具有包括边缘区域的主表面和具有包括对应于器件晶片的边缘区域的环形表面区域的另外的主表面的载体的器件晶片。 粘合剂施加在边缘区域和/或环形表面区域中，但不施加在主表面的剩余区域上。 器件晶片通过粘合剂固定到载体上。 当装置晶片被固定到载体上时，主表面和另外的主表面彼此接触，而主表面和另外的主表面仅在边缘区域彼此紧固。 在进一步的工艺步骤之后，器件晶片从载体上移除，其可以包括在器件晶片中形成贯通晶片通孔。

    SEMICONDUCTOR DEVICE WITH THROUGH-SUBSTRATE VIA
    3.
    发明申请
    SEMICONDUCTOR DEVICE WITH THROUGH-SUBSTRATE VIA 有权

    公开(公告)号：US20210175153A1

    公开(公告)日：2021-06-10

    申请号：US17052452

    申请日：2019-03-20

    Applicant: ams AG

    Inventor： Jochen KRAFT ,  Georg PARTEDER ,  Anderson PIRES SINGULANI ,  Raffaele COPPETA ,  Franz SCHRANK

    IPC: H01L23/48 ,  H01L23/00 ,  H01L23/528

    Abstract: A semiconductor device includes a semiconductor body, an electrically conductive via which extends through at least a part of the semiconductor body, and where the via has a top side and a bottom side that faces away from the top side, an electrically conductive etch-stop layer arranged at the bottom side of the via in a plane which is parallel to a lateral direction, where the lateral direction is perpendicular to a vertical direction given by the main axis of extension of the via, and at least one electrically conductive contact layer at the bottom side of the via in a plane which is parallel to the lateral direction. The etch-stop layer is arranged between the electrically conductive via and the contact layer in the vertical direction, the lateral extent in the lateral direction of the etch-stop layer amounts to at least 2.5 times the lateral extent of the via in the lateral direction, and the lateral extent of the contact layer is smaller than the lateral extent of the via or the lateral extent of the contact layer amounts to at least 2.5 times the lateral extent of the via.

    METHOD OF PRODUCING A SEMICONDUCTOR DEVICE HAVING AN INTERCONNECT THROUGH THE SUBSTRATE
    4.
    发明申请
    METHOD OF PRODUCING A SEMICONDUCTOR DEVICE HAVING AN INTERCONNECT THROUGH THE SUBSTRATE 有权
    生产通过基板的互连的半导体器件的方法

    公开(公告)号：US20140038410A1

    公开(公告)日：2014-02-06

    申请号：US13956274

    申请日：2013-07-31

    Applicant: ams AG

    Inventor： Jochen KRAFT ,  Franz SCHRANK ,  Martin SCHREMS

    IPC: H01L21/768

    CPC classification number: H01L21/76898 ,  H01L21/76831 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A semiconductor substrate (1) is provided on a main surface (14) with an intermetal dielectric (4) including metal planes (5) and on an opposite rear surface (15) with an insulation layer (2) and an electrically conductive connection pad (7). An etch stop layer (6) is applied on the intermetal dielectric to prevent a removal of the intermetal dielectric above the metal planes during subsequent method steps. An opening (9) having a side wall (3) and a bottom (13) is formed from the main surface through the substrate above the connection pad. A side wall spacer (10) is formed on the side wall by a production and subsequent partial removal of a dielectric layer (11). The insulation layer is removed from the bottom to uncover an area of the connection pad. A metal layer is applied in the opening and is provided for an interconnect through the substrate.

    Abstract translation: 在具有包括金属平面（5）的金属间电介质（4）和具有绝缘层（2）的相对后表面（15）的主表面（14）上设置半导体基板（1）和导电连接垫 （7）。 在金属间电介质上施加蚀刻停止层（6），以防止在随后的方法步骤期间去除金属平面之上的金属间电介质。 具有侧壁（3）和底部（13）的开口（9）通过连接垫上方的基板从主表面形成。 通过产生并随后部分去除电介质层（11），在侧壁上形成侧壁间隔物（10）。 绝缘层从底部移除以露出连接垫的一个区域。 金属层被施加在开口中并且被提供用于通过基底的互连。

    SEMICONDUCTOR DEVICE WITH PHOTONIC AND ELECTRONIC FUNCTIONALITY AND METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE
    5.
    发明申请
    SEMICONDUCTOR DEVICE WITH PHOTONIC AND ELECTRONIC FUNCTIONALITY AND METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20190025505A1

    公开(公告)日：2019-01-24

    申请号：US15757645

    申请日：2016-08-25

    Applicant: ams AG

    Inventor： Jochen KRAFT ,  Joerg SIEGERT

    IPC: G02B6/12 ,  H01L23/522 ,  H01L21/48 ,  H01L23/00 ,  G02B6/13

    Abstract: A semiconductor device has a semiconductor substrate and a first metallization stack arranged on the substrate. The substrate has and/or carries a plurality of electronic circuit elements. The first metallization stack has electrically insulating layers and at least one metallization layer. The semiconductor device further has a second metallization stack arranged on the first metallization stack and comprising further electrically insulating layers and an optical waveguide layer. The optical waveguide layer has at least one optical waveguide structure. Furthermore, one of the electrically insulating layers and one of the further electrically insulating layers are in direct contact with each other and form a pair of directly bonded layers.

    SEMICONDUCTOR DEVICE WITH INTEGRATED MIRROR AND METHOD OF PRODUCING A SEMICONDUCTOR DEVICE WITH INTEGRATED MIRROR
    6.
    发明申请
    SEMICONDUCTOR DEVICE WITH INTEGRATED MIRROR AND METHOD OF PRODUCING A SEMICONDUCTOR DEVICE WITH INTEGRATED MIRROR 有权
    具有集成镜的半导体器件及其制造具有集成反射镜的半导体器件的方法

    公开(公告)号：US20160334572A1

    公开(公告)日：2016-11-17

    申请号：US15101406

    申请日：2014-11-17

    Applicant: AMS AG

    Inventor： Jochen KRAFT ,  Joerg SIEGERT ,  Ewald STUECKLER

    IPC: G02B6/122 ,  G02B6/132

    CPC classification number: G02B6/122 ,  G02B6/12004 ,  G02B6/132 ,  G02B6/136 ,  G02B6/4214 ,  G02B6/43 ,  G02B2006/12104

    Abstract: The semiconductor device comprises a substrate (1) of semiconductor material, a dielectric layer (2) above the substrate, a waveguide (3) arranged in the dielectric layer, and a mirror region (4) arranged on a surface of a mirror support (5) integrated on the substrate. A mirror is thus formed facing the waveguide. The surface of the mirror support and hence the mirror are inclined with respect to the waveguide.

    Abstract translation: 半导体器件包括半导体材料的衬底（1），衬底上的电介质层（2），布置在电介质层中的波导（3）和布置在反射镜支撑体的表面上的反射镜区域（4） 5）集成在基板上。 因此形成面向波导的反射镜。 反射镜支撑体的表面，因此反射镜相对于波导管倾斜。

    SEMICONDUCTOR DEVICE WITH THROUGH-SUBSTRATE VIA AND CORRESPONDING METHOD OF MANUFACTURE
    7.
    发明申请
    SEMICONDUCTOR DEVICE WITH THROUGH-SUBSTRATE VIA AND CORRESPONDING METHOD OF MANUFACTURE 审中-公开
    具有通过基板的半导体器件和相应的制造方法

    公开(公告)号：US20160322519A1

    公开(公告)日：2016-11-03

    申请号：US15107901

    申请日：2014-12-12

    Applicant: AMS AG

    Inventor： Franz SCHRANK ,  Sara CARNIELLO ,  Hubert ENICHLMAIR ,  Jochen KRAFT ,  Bernhard LOEFFLER ,  Rainer HOLZHAIDER

    IPC: H01L31/0224 ,  H01L31/103 ,  H01L31/18 ,  H01L31/0216

    Abstract: A dielectric layer (2) is arranged on the main surface (10) of a semiconductor substrate (1), and a passivation layer (6) is arranged on the dielectric layer. A metal layer (3) is embedded in the dielectric layer above an opening (12) in the substrate, and a metallization (14) is arranged in the opening. The metallization contacts the metal layer and forms a through-substrate via to a rear surface (11) of the substrate. A layer or layer sequence (7, 8, 9) comprising at least one further layer is arranged on the passivation layer above the opening. In this way the bottom of the through-substrate via is stabilized. A plug (17) may additionally be arranged in the opening without filling the opening.

    Abstract translation: 在半导体衬底（1）的主表面（10）上布置介电层（2），并且在介质层上布置钝化层（6）。 金属层（3）嵌入基板中的开口（12）上方的电介质层中，并且金属化层（14）布置在开口中。 金属化接触金属层，并通过基板的后表面（11）形成贯穿基板。 包含至少一个另外的层的层或层序列（7,8,9）布置在开口上方的钝化层上。 以这种方式，穿透基底通孔的底部是稳定的。 插头（17）还可以布置在开口中而不填充开口。

    THROUGH-SUBSTRATE VIA AND METHOD FOR MANUFACTURING A THROUGH-SUBSTRATE VIA
    8.
    发明申请
    THROUGH-SUBSTRATE VIA AND METHOD FOR MANUFACTURING A THROUGH-SUBSTRATE VIA 有权

    公开(公告)号：US20220328380A1

    公开(公告)日：2022-10-13

    申请号：US17639736

    申请日：2020-08-27

    Applicant: ams AG

    Inventor： Georg PARTEDER ,  Jochen KRAFT ,  Stefan JESSENIG

    IPC: H01L23/48 ,  H01L21/768

    Abstract: An open through-substrate via, TSV, comprises an insulation layer disposed adjacent to at least a portion of side walls of a trench and to a surface of a substrate body. The TSV further comprises a metallization layer disposed adjacent to at least a portion of the insulation layer and to at least a portion of a bottom wall of said trench, a redistribution layer disposed adjacent to at least a portion of the metallization layer and a portion of the insulation layer disposed adjacent to the surface, and a capping layer disposed adjacent to at least a portion of the metallization layer and to at least a portion of the redistribution layer. The insulation layer and/or the capping layer comprise sublayers that are distinct from each other in terms of material properties. A first of the sublayers is disposed adjacent to at least a portion of the side walls and to at least a portion of the surface and a second of the sublayers is disposed adjacent to at least a portion of the surface.

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