公开(公告)号：US20180096969A1

公开(公告)日：2018-04-05

申请号：US15726905

申请日：2017-10-06

Applicant: ams AG

Inventor： Jochen KRAFT ,  Martin SCHREMS ,  Franz SCHRANK

IPC: H01L25/065 ,  H01L25/00 ,  H01L23/00 ,  H01L21/683 ,  H01L23/498 ,  H01L23/48 ,  H01L23/538 ,  H01L23/14 ,  H01L21/56 ,  H01L21/48

CPC classification number: H01L25/0655 ,  H01L21/486 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/147 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/82 ,  H01L24/85 ,  H01L24/92 ,  H01L24/94 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68372 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05548 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/13024 ,  H01L2224/1403 ,  H01L2224/16145 ,  H01L2224/16147 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/24146 ,  H01L2224/24147 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45099 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73259 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/82 ,  H01L2224/82005 ,  H01L2224/82031 ,  H01L2224/83005 ,  H01L2224/85 ,  H01L2224/85005 ,  H01L2224/9222 ,  H01L2224/92242 ,  H01L2224/92244 ,  H01L2224/92247 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06506 ,  H01L2225/06524 ,  H01L2225/06544 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2924/10155 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/157 ,  H01L2924/00012 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/207

Abstract: The method of producing an interposer-chip-arrangement, comprises providing an interposer (1) with an integrated circuit (25), arranging a dielectric layer (2) with metal layers embedded in the dielectric layer above a main surface (10) of the interposer, connecting the integrated circuit with at least one of the metal layers, forming an interconnection (7) through the interposer, the interconnection contacting one of the metal layers, arranging a further dielectric layer (3) above a further main surface (11) of the interposer opposite the main surface and arranging a further metal layer in or on the further dielectric layer, the further metal layer being connected with the interconnection, arranging a chip provided with at least one contact pad at the main surface or at the further main surface, and electrically conductively connecting the contact pad with the interconnection.

公开(公告)号：US20160035929A1

公开(公告)日：2016-02-04

申请号：US14777484

申请日：2014-03-11

Applicant: AMS AG

Inventor： Jordi TEVA ,  Frederic ROGER ,  Ewald STUECKLER ,  Stefan JESSENIG ,  Rainer MINIXHOFER ,  Ewald WACHMANN ,  Martin SCHREMS ,  Guenther KOPPITSCH

IPC: H01L31/107 ,  H01L31/18 ,  H01L31/0368 ,  H01L31/0224 ,  H01L31/0352

CPC classification number: H01L31/107 ,  H01L31/022408 ,  H01L31/03529 ,  H01L31/03682 ,  H01L31/182 ,  Y02E10/50

Abstract: The lateral single-photon avalanche diode comprises a semiconductor body comprising a semiconductor material of a first type of electric conductivity, a trench in the semiconductor body, and anode and cathode terminals. A junction region of the first type of electric conductivity is located near the sidewall of the trench, and the electric conductivity is higher in the junction region than at a farther distance from the sidewall. A semiconductor layer of an opposite second type of electric conductivity is arranged at the sidewall of the trench adjacent to the junction region. The anode and cathode terminals are electrically connected with the semiconductor layer and with the junction region, respectively. The junction region may be formed by a sidewall implantation.

Abstract translation: 横向单光子雪崩二极管包括半导体本体，其包括第一导电类型的半导体材料，半导体主体中的沟槽以及阳极和阴极端子。 第一类电导率的结区域位于沟槽的侧壁附近，并且在结区域中的电导率高于距离侧壁更远的距离。 相邻的第二导电类型的半导体层被布置在与结区相邻的沟槽的侧壁处。 阳极和阴极端子分别与半导体层和结区域电连接。 接合区域可以通过侧壁注入形成。

公开(公告)号：US20190312076A1

公开(公告)日：2019-10-10

申请号：US16309226

申请日：2017-06-13

Applicant: ams AG

Inventor： Martin SCHREMS ,  Thomas STOCKMEIER

IPC: H01L27/146 ,  G02B5/20

Abstract: The system-on-chip camera comprises a semiconductor body (1) with an integrated circuit (40), a sensor substrate (2), sensor elements (3) arranged in the sensor substrate according to an array of pixels, a light sensor (4) in the sensor substrate apart from the sensor elements, and a lens or an array of lenses (15) on a surface of incidence (30). Filter elements (11, 12, 13), which may especially be interference filters for red, green or blue, are arranged between the sensor elements and the surface of incidence.

公开(公告)号：US20170309665A1

公开(公告)日：2017-10-26

申请号：US15528089

申请日：2015-11-09

Applicant: ams AG

Inventor： Joerg SIEGERT ,  Franz SCHRANK ,  Martin SCHREMS

IPC: H01L27/146

CPC classification number: H01L27/14623 ,  H01L23/481 ,  H01L27/1462 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14636 ,  H01L27/14645 ,  H01L27/14685

Abstract: A photosensor (2) is arranged in a semiconductor substrate (1) at a main surface (10), a dielectric layer (4) is arranged on or above the main surface, the dielectric layer including a metal layer (6) electrically connected with the photosensor, and an aperture layer (16) formed from an opaque or semitransparent material is arranged on or above the dielectric layer. The aperture layer is provided with an array of transparent aperture zones (18) above the photosensor, each of the aperture zones penetrating the aperture layer.

公开(公告)号：US20170179056A1

公开(公告)日：2017-06-22

申请号：US15118469

申请日：2015-02-09

Applicant: Ams AG

Inventor： Martin SCHREMS ,  Bernhard STERING ,  Harald ETSCHMAIER

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/485

CPC classification number: H01L24/11 ,  H01L23/31 ,  H01L23/3157 ,  H01L23/481 ,  H01L23/485 ,  H01L23/562 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/14 ,  H01L2224/02125 ,  H01L2224/03001 ,  H01L2224/0401 ,  H01L2224/05551 ,  H01L2224/05555 ,  H01L2224/05563 ,  H01L2224/0557 ,  H01L2224/05573 ,  H01L2224/05576 ,  H01L2224/05599 ,  H01L2224/13023 ,  H01L2224/13025 ,  H01L2224/13027 ,  H01L2224/131 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: The semiconductor device comprises a semiconductor substrate (1) with a main surface (10) and a further main surface (11) opposite the main surface, a TSV (3) penetrating the substrate from the main surface to the further main surface, a metallization (13) of the TSV, an under-bump metallization (5) and a bump contact (6) at least partially covering the TSV at the further main surface. The TSV (3) comprises a cavity (15), which may be filled with a gas or liquid. An opening (15′) of the cavity is provided to expose the cavity to the environment.

公开(公告)号：US20170018518A1

公开(公告)日：2017-01-19

申请号：US15283189

申请日：2016-09-30

Applicant: ams AG

Inventor： Cathal CASSIDY ,  Martin SCHREMS ,  Franz SCHRANK

IPC: H01L23/00

CPC classification number: H01L23/5226 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5283 ,  H01L23/53295 ,  H01L23/552 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/10125 ,  H01L2224/11334 ,  H01L2224/11849 ,  H01L2224/13025 ,  H01L2224/13027 ,  H01L2224/13028 ,  H01L2224/131 ,  H01L2224/1319 ,  H01L2224/13561 ,  H01L2224/1357 ,  H01L2224/136 ,  H01L2224/16106 ,  H01L2224/1613 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/00014 ,  H01L2924/30101 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/05552

Abstract: A semiconductor substrate is provided with a through-substrate via comprising a metallization and an opening. A solder ball is placed on the opening. A reflow of the solder ball is performed in such a way that the solder ball closes the through-substrate via and leaves a void in the through-substrate via.

Abstract translation: 半导体衬底设置有包括金属化和开口的贯穿衬底通孔。 焊球放置在开口处。 焊球的回流以这样的方式进行，使得焊球闭合贯穿基板通孔，并在通孔中留下空隙。

公开(公告)号：US20220328551A1

公开(公告)日：2022-10-13

申请号：US17851980

申请日：2022-06-28

Applicant: ams AG

Inventor： Martin SCHREMS ,  Thomas STOCKMEIER

IPC: H01L27/146 ,  G02B5/20

Abstract: The system-on-chip camera comprises a semiconductor body with an integrated circuit, a sensor substrate, sensor elements arranged in the sensor substrate according to an array of pixels, a light sensor in the sensor substrate apart from the sensor elements, and a lens or an array of lenses on a surface of incidence. Filter elements, which may especially be interference filters for red, green or blue, are arranged between the sensor elements and the surface of incidence.

公开(公告)号：US20170062504A1

公开(公告)日：2017-03-02

申请号：US15119377

申请日：2015-02-10

Applicant: ams AG

Inventor： Rainer MINIXHOFER ,  Martin SCHREMS ,  Sara CARNIELLO

IPC: H01L27/146

CPC classification number: H01L27/1464 ,  H01L27/14618 ,  H01L27/14627 ,  H01L27/14629 ,  H01L27/14632 ,  H01L27/14634 ,  H01L27/14645 ,  H01L27/14649 ,  H01L27/14687 ,  H01L27/14689 ,  H01L27/1469 ,  H01L27/3269 ,  H01L31/02016 ,  H01L31/0203 ,  H01L2924/1815

Abstract: The semiconductor device comprises a semiconductor substrate (1), a sensor or sensor array (2) arranged at a main surface (10) of the substrate, an integrated circuit (3) arranged at or above the main surface, and a focusing element (17) comprising recesses (4) formed within a further main surface (11) of the substrate opposite the main surface. The focusing element may be arranged opposite the sensor or sensor array (2), which may be a photosensor or photodetector or an array of photosensors or photodetectors, for instance. The focusing element (17) is formed by etching the recesses (4) into the semiconductor material.

Abstract translation: 半导体器件包括半导体衬底（1），布置在衬底的主表面（10）处的传感器或传感器阵列（2），布置在主表面上或上方的集成电路（3）和聚焦元件 17）包括形成在与主表面相对的基板的另一主表面（11）内的凹部（4）。 聚焦元件可以布置成与传感器或传感器阵列（2）相对，例如可以是光电传感器或光电检测器或光电传感器或光电探测器阵列。 通过将凹部（4）蚀刻成半导体材料形成聚焦元件（17）。

公开(公告)号：US20160104741A1

公开(公告)日：2016-04-14

申请号：US14889835

申请日：2014-04-15

Applicant: ams AG

Inventor： Hubert ENICHLMAIR ,  Rainer MINIXHOFER ,  Martin SCHREMS

IPC: H01L27/146 ,  H01L31/0368

CPC classification number: H01L27/14649 ,  G01J5/022 ,  G01J5/0225 ,  G01J5/024 ,  G01J5/045 ,  G01J5/048 ,  G01J5/0806 ,  G01J2005/0077 ,  H01L27/14618 ,  H01L27/14625 ,  H01L27/14636 ,  H01L27/14685 ,  H01L31/02325 ,  H01L31/03682 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The integrated imaging device comprises a substrate (1) with an integrated circuit (4), a cover (2), a cavity (6) enclosed between the substrate (1) and the cover (2), and a sensor (5) or an array of sensors (5) arranged in the cavity (6). A surface (11, 12) of the substrate (1) or the cover (2) opposite the cavity (6) has a structure (8) directing incident radiation. The surface structure (8) may be a plate zone or a Fresnel lens focusing infrared radiation and may be etched into the surface of the substrate or cover, respectively.

Abstract translation: 集成成像装置包括具有集成电路（4），盖（2），封闭在基板（1）和盖（2）之间的空腔（6）的基板（1）和传感器（5）或 布置在空腔（6）中的传感器阵列（5）。 衬底（1）或与腔（6）相对的盖（2）的表面（11,12）具有引导入射辐射的结构（8）。 表面结构（8）可以是聚焦红外辐射的平板区域或菲涅耳透镜，并且可以分别蚀刻到基底或盖的表面中。

公开(公告)号：US20150303141A1

公开(公告)日：2015-10-22

申请号：US14651197

申请日：2013-12-05

Applicant: AMS AG

Inventor： Franz SCHRANK ,  Martin SCHREMS

IPC: H01L23/528 ,  G01N27/14 ,  G01N33/00 ,  H01L23/522

CPC classification number: H01L23/528 ,  G01N27/128 ,  G01N27/14 ,  G01N33/0004 ,  G01N33/0016 ,  H01L21/76898 ,  H01L23/345 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/647 ,  H01L27/0629 ,  H01L31/024 ,  H01L2223/6672 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The semiconductor device comprises a substrate of semiconductor material, a dielectric layer on the substrate, an electrically conductive contact pad arranged in the dielectric layer, a hot plate arranged in the dielectric layer, a recess of the substrate at the location of the hot plate, and an integrated circuit, which operates the hot plate. An electrically conductive layer is arranged on a side of the substrate opposite the dielectric layer. The substrate is provided with a via hole above the contact pad, and an electrically conductive material connecting the electrically conductive layer with the contact pad is applied in the via hole. The recess and the via hole are formed in the same process step.

Abstract translation: 半导体器件包括半导体材料的衬底，衬底上的电介质层，布置在电介质层中的导电接触焊盘，布置在电介质层中的热板，在热板的位置处的衬底的凹部， 以及操作热板的集成电路。 导电层布置在与电介质层相对的衬底的一侧上。 衬底在接触焊盘上方设置有通孔，并且将导电层与接触焊盘连接的导电材料施加在通孔中。 凹槽和通孔在相同的工艺步骤中形成。