公开(公告)号：US20240290883A1

公开(公告)日：2024-08-29

申请号：US18441808

申请日：2024-02-14

Applicant: Applied Materials, Inc.

Inventor： Sai Hooi Yeong ,  Hui Zhao ,  Ashish Pal ,  El Mehdi Bazizi ,  Benjamin Colombeau ,  Balasubramanian Pranatharthiharan ,  Lequn Liu

IPC: H01L29/78 ,  H01L21/762 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/7846 ,  H01L21/76224 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78696

Abstract: The present technology includes semiconductor devices with improved stress in a channel region. The semiconductor device includes a substrate, a source region, a drain region, a channel region that includes at least one channel located between the source and the drain, a first gate region, and a second gate region. The first gate region includes a self-aligned single diffusion break, and the second gate region includes a first gate enclosing the channel between the source region and the drain region. The self-aligned single diffusion break also contains a dielectric liner and a stressed metal fill, where the stressed metal fill exhibits a stress of about 350 MPa or greater.

公开(公告)号：US20240234544A1

公开(公告)日：2024-07-11

申请号：US18538267

申请日：2023-12-13

Applicant: Applied Materials, Inc.

Inventor： Sai Hooi Yeong ,  Benjamin Colombeau ,  Liu Jiang ,  El Mehdi Bazizi ,  Byeong Chan Lee ,  Balasubramanian Pranatharthiharan

IPC: H01L29/66 ,  C23C16/02 ,  C23C16/04 ,  C23C16/32 ,  C23C16/40 ,  C23C16/56 ,  C30B25/04 ,  C30B25/18 ,  C30B29/06 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/66553 ,  C23C16/0227 ,  C23C16/045 ,  C23C16/325 ,  C23C16/401 ,  C23C16/56 ,  C30B25/04 ,  C30B25/186 ,  C30B29/06 ,  H01L29/0673 ,  H01L29/41775 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/78696

Abstract: Semiconductor devices (e.g., gate-all-around (GAA) devices), process tools for manufacturing GAA devices and methods of manufacturing GAA devices, and inner spacer liners and inner spacers for GAA devices, are described. The methods comprise forming an inner spacer liner within a superlattice structure formed on a top surface of a semiconductor substrate. The superlattice structure has a plurality of recessed semiconductor material layers (e.g., silicon germanium (SiGe)) and a corresponding plurality of channel layers (e.g., silicon (Si)) alternatingly arranged in a plurality of stacked pairs. The inner spacer liner comprises a crystalline silicon-containing liner formed by a selective epitaxial growth (SEG) process. The crystalline silicon-containing liner may be doped with a dopant (e.g., a p-type dopant or an n-type dopant). One or more operations of the methods described herein are performed in situ in an integrated processing tool system.

公开(公告)号：US20240194757A1

公开(公告)日：2024-06-13

申请号：US18383182

申请日：2023-10-24

Applicant: Applied Materials, Inc.

Inventor： Sai Hooi Yeong ,  Liu Jiang ,  Susmit Singha Roy ,  Abhijit Basu Mallick ,  El Mehdi Bazizi ,  Benjamin Colombeau

IPC: H01L29/423 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/42392 ,  H01L21/823807 ,  H01L21/823864 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/775 ,  H01L29/78696

Abstract: Semiconductor devices (e.g., gate-all-around (GAA) devices), process tools for manufacturing GAA devices and methods of manufacturing GAA devices and multilayer inner spacers for GAA devices are described. The multilayer inner spacer comprises an inner layer, a middle layer, and an outer layer within a superlattice structure formed on a top surface of a substrate. The superlattice structure has a plurality of semiconductor material layers (e.g., silicon germanium (SiGe)) and a corresponding plurality of channel layers (e.g., silicon (Si)) alternatingly arranged in a plurality of stacked pairs. In some embodiments, the methods are performed in situ in an integrated deposition and etch processing system.

公开(公告)号：US20240120193A1

公开(公告)日：2024-04-11

申请号：US17960569

申请日：2022-10-05

Applicant: Applied Materials, Inc.

Inventor： Shankar Venkataraman ,  Zeqing Shen ,  Susmit Singha Roy ,  Abhijit Basu Mallick ,  Lakmal C. Kalutarage ,  Jongbeom Seo ,  Sai Hooi Yeong ,  Benjamin Colombeau ,  Balasubramanian Pranatharthiharan

IPC: H01L21/02 ,  H01L21/311 ,  H01L29/66

CPC classification number: H01L21/02126 ,  H01L21/0206 ,  H01L21/02211 ,  H01L21/02222 ,  H01L21/02274 ,  H01L21/31116 ,  H01L29/66439 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/42392

Abstract: Exemplary methods of semiconductor processing may include etching a portion of a silicon-containing material from a substrate disposed within a processing region of a semiconductor processing chamber. The silicon-containing material may extend into one or more recesses defined by alternating layers of material deposited on the substrate. The methods may include providing a carbon-containing precursor to the processing region of the semiconductor processing chamber. The methods may include contacting a remaining silicon-containing material with the carbon-containing precursor. The contacting with the carbon-containing precursor may replenish carbon in the silicon-containing material. The methods may include providing a cleaning agent to the processing region of the semiconductor processing chamber. The methods may include contacting the substrate with the cleaning agent. The contacting with the cleaning precursor may remove surface oxide from the substrate.

公开(公告)号：US20220375753A1

公开(公告)日：2022-11-24

申请号：US17882177

申请日：2022-08-05

Applicant: Applied Materials, Inc.

Inventor： Wolfgang Aderhold ,  Yi-Chiau Huang ,  Wei Liu ,  Benjamin Colombeau ,  Abhilash Mayur

IPC: H01L21/225 ,  H01L21/324

Abstract: A method of selectively and conformally doping semiconductor materials is disclosed. Some embodiments utilize a conformal dopant film deposited selectively on semiconductor materials by thermal decomposition. Some embodiments relate to doping non-line of sight surfaces. Some embodiments relate to methods for forming a highly doped crystalline semiconductor layer.

公开(公告)号：US11508828B2

公开(公告)日：2022-11-22

申请号：US17354251

申请日：2021-06-22

Applicant: Applied Materials, Inc.

Inventor： Michael Stolfi ,  Myungsun Kim ,  Benjamin Colombeau ,  Sanjay Natarajan

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L27/088

Abstract: Horizontal gate-all-around devices and methods of manufacturing same are described. The hGAA devices comprise a trimmed semiconductor material between source regions and drain regions of the device. The method includes selectively isotropically etching semiconductor material layers between source regions and drain regions of an electronic device.

公开(公告)号：US11456178B2

公开(公告)日：2022-09-27

申请号：US17348081

申请日：2021-06-15

Applicant: Applied Materials, Inc.

Inventor： Steven C. H. Hung ,  Benjamin Colombeau ,  Abhishek Dube ,  Sheng-Chin Kung ,  Patricia M. Liu ,  Malcolm J. Bevan ,  Johanes F. Swenberg

IPC: H01L21/28 ,  H01L21/02 ,  H01L21/321 ,  H01L21/8234

Abstract: Processing methods may be performed to produce semiconductor structures. The methods may include forming a silicon layer over a semiconductor substrate. The forming may include forming a silicon layer incorporating a dopant. The methods may include oxidizing a portion of the silicon layer while maintaining a portion of the silicon layer in contact with the semiconductor substrate. The oxidizing may drive a portion of the dopant through the silicon layer and into the semiconductor substrate.

公开(公告)号：US20220037147A1

公开(公告)日：2022-02-03

申请号：US17386724

申请日：2021-07-28

Applicant: Applied Materials, Inc.

Inventor： Myungsun Kim ,  Jingmei Liang ,  Martin J. Seamons ,  Michael Stolfi ,  Benjamin Colombeau

IPC: H01L21/02 ,  H01L29/66 ,  H01L21/311 ,  H01L27/12

Abstract: Provided are methods of depositing a film in high aspect ratio (AR) structures with small dimensions. The method provides flowable deposition for seamless gap-fill, film densification by low temperature inductively coupled plasma (ICP) treatment (

公开(公告)号：US11024746B2

公开(公告)日：2021-06-01

申请号：US16818259

申请日：2020-03-13

Applicant: Applied Materials, Inc.

Inventor： Russell Chin Yee Teo ,  Benjamin Colombeau

IPC: H01L29/786 ,  H01L27/06 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L21/02 ,  H01L21/28 ,  H01L21/822

Abstract: Gate all-around devices are disclosed in which an angled channel comprising a semiconducting nanostructure is located between a source and a drain. The angled channel has an axis that is oriented at an angle to the top surface of the substrate at an angle in a range of about 1° to less than about 90°. The gate all-around device is intended to meet design and performance criteria for the 7 nm technology generation.

公开(公告)号：US10861722B2

公开(公告)日：2020-12-08

申请号：US16579756

申请日：2019-09-23

Applicant: Applied Materials, Inc.

Inventor： Benjamin Colombeau ,  Sheng-Chin Kung ,  Patricia M. Liu

IPC: H01L21/67 ,  H01L21/3065 ,  H01L21/02 ,  H01L29/165 ,  H01L29/40 ,  H01L29/66 ,  H01L29/423

Abstract: Generally, examples described herein relate to integrated solutions for forming cladding layers on trimmed layers that were formed as part of a superlattice. In an example, a first material is selectively etched in a first processing chamber of a processing system. The first material is disposed within alternating layers of the first material and a second material in a channel region on a substrate. A portion of the second material is trimmed in the first processing chamber of the processing system. The substrate is transferred from the first processing chamber of the processing system to a second processing chamber of the processing system without exposing the substrate to an ambient environment exterior to the processing system. A cladding layer is epitaxially grown on respective layers of the trimmed second material in the second processing chamber of the processing system.