公开(公告)号：US4654115A

公开(公告)日：1987-03-31

申请号：US849247

申请日：1986-04-08

申请人： Frank D. Egitto ,  Francis Emmi ,  Walter E. Mlynko ,  Robin A. Susko

发明人： Frank D. Egitto ,  Francis Emmi ,  Walter E. Mlynko ,  Robin A. Susko

IPC分类号： B08B3/08 ,  H01L21/302 ,  H01L21/304 ,  H01L21/3065 ,  H05K3/00 ,  H05K3/08 ,  H05K3/26 ,  H05K3/42 ,  B44C1/22 ,  B29C37/00 ,  C03C15/00 ,  C03C25/06

CPC分类号： H05K3/0055 ,  H05K2203/095

摘要： Contaminant is removed from holes by etching in a gaseous plasma by first removing contaminant from the vicinity of the edges of the hole. Next, a mask is provided in the vicinity of the edges to prevent etching by contacting with a gaseous plasma which is different from the gaseous plasma employed in the first etching step. The holes are then etched in a gaseous plasma to remove contaminant from the interior of the holes in the vicinity of the center of the holes, whereby the mask protects the edges from being etched.

摘要翻译： 通过首先从孔的边缘附近去除污染物，通过在气态等离子体中蚀刻从孔中除去污染物。 接下来，在边缘附近设置掩模，以防止与不同于在第一蚀刻步骤中使用的气态等离子体接触的气体等离子体进行蚀刻。 然后在气体等离子体中蚀刻孔，以从孔的中心附近的孔的内部除去污染物，由此掩模保护边缘不被蚀刻。

公开(公告)号：US5110409A

公开(公告)日：1992-05-05

申请号：US631866

申请日：1990-12-21

申请人： Frank D. Egitto ,  Walter E. Mlynko

发明人： Frank D. Egitto ,  Walter E. Mlynko

IPC分类号： H01L21/311 ,  H05K3/00

CPC分类号： H01L21/31138 ,  H05K3/0017

摘要： Increased etching rates are obtained by plasma etching wherein the power is applied in a cyclical or oscillating mode.

摘要翻译： 通过等离子体蚀刻获得增加的蚀刻速率，其中功率以循环或振荡模式施加。

公开(公告)号：US4985112A

公开(公告)日：1991-01-15

申请号：US12696

申请日：1987-02-09

申请人： Frank D. Egitto ,  Walter E. Mlynko

发明人： Frank D. Egitto ,  Walter E. Mlynko

IPC分类号： H01L21/302 ,  H01L21/3065 ,  H01L21/311 ,  H05K3/00

CPC分类号： H01L21/31138 ,  H05K3/0017

摘要： Increased etching rates are obtained by plasma etching wherein the power is applied in a cyclical or oscillating mode.

公开(公告)号：US09351408B2

公开(公告)日：2016-05-24

申请号：US12764997

申请日：2010-04-22

申请人： Voya Markovich ,  Timothy Antesberger ,  Frank D. Egitto ,  William Wilson ,  Rabindra N. Das

发明人： Voya Markovich ,  Timothy Antesberger ,  Frank D. Egitto ,  William Wilson ,  Rabindra N. Das

IPC分类号： H05K1/09 ,  H05K1/03 ,  H05K3/40

CPC分类号： H05K3/4069 ,  H05K3/4614 ,  H05K3/462 ,  H05K3/4623 ,  H05K2203/063

摘要： A substrate for use in a PCB or PWB board having a coreless buildup layer and at least one metal and at least one dielectric layer. The coreless buildup dielectric layers can consist of at least partially cured thermoset resin and thermoplastic resin. The substrate may also contain land grid array (LGA) packaging.

摘要翻译： 一种用于PCB或PWB板的衬底，其具有无芯堆积层和至少一个金属和至少一个介电层。 无芯堆积电介质层可由至少部分固化的热固性树脂和热塑性树脂组成。 衬底还可以包含焊盘阵列（LGA）封装。

公开(公告)号：US08536459B2

公开(公告)日：2013-09-17

申请号：US12764994

申请日：2010-04-22

申请人： Voya Markovich ,  Timothy Antesberger ,  Frank D. Egitto ,  William Wilson ,  Rabindra N. Das

发明人： Voya Markovich ,  Timothy Antesberger ,  Frank D. Egitto ,  William Wilson ,  Rabindra N. Das

IPC分类号： H05K1/03 ,  H05K1/02 ,  H05K1/09

CPC分类号： H05K3/4623 ,  H05K1/092 ,  H05K3/4053 ,  H05K3/4614 ,  H05K3/4691 ,  H05K2203/061

摘要： A substrate for use in a PCB or PWB board having a coreless buildup layer and at least one metal and at least one dielectric layer. The coreless buildup dielectric layers can consist of at least partially cured thermoset resin and thermoplastic resin. The substrate may also contain land grid array (LGA) packaging.

摘要翻译： 一种用于PCB或PWB板的衬底，其具有无芯堆积层和至少一个金属和至少一个介电层。 无芯堆积电介质层可由至少部分固化的热固性树脂和热塑性树脂组成。 衬底还可以包含焊盘阵列（LGA）封装。

公开(公告)号：US07875811B2

公开(公告)日：2011-01-25

申请号：US12010335

申请日：2008-01-24

申请人： David V. Caletka ,  Frank D. Egitto

发明人： David V. Caletka ,  Frank D. Egitto

IPC分类号： H01R12/04 ,  H05K1/11

CPC分类号： H05K1/0219 ,  H01R12/523 ,  H01R13/2414 ,  H05K1/113 ,  H05K3/4046 ,  H05K3/429 ,  H05K3/4614 ,  H05K2201/0959 ,  H05K2201/09809 ,  H05K2201/10303 ,  H05K2201/10378 ,  Y10T29/49155 ,  Y10T29/49165

摘要： A high speed interposer which includes a substrate having alternatingly oriented dielectric and conductive layers which form a substrate, openings which extend from one opposing surface of the substrate to a second opposing surface, conductive members positioned within the openings and also extending from surface to surface (and beyond, in some embodiments), and a plurality of shielding members positioned substantially around the conductive members to provide shielding therefore during the passage of high frequency signals through the conductive members.

摘要翻译： 高速插入器，其包括具有交替取向的介电层和导电层的基板，其形成基板，从基板的一个相对表面延伸到第二相对表面的开口，定位在开口内并且还从表面延伸到表面的导电构件 并且在一些实施例中超越）以及基本上围绕导电构件定位的多个屏蔽构件，从而在高频信号通过导电构件期间提供屏蔽。

公开(公告)号：US07800916B2

公开(公告)日：2010-09-21

申请号：US11783306

申请日：2007-04-09

申请人： Kim J. Blackwell ,  Frank D. Egitto ,  John M. Lauffer ,  Voya R. Markovich

发明人： Kim J. Blackwell ,  Frank D. Egitto ,  John M. Lauffer ,  Voya R. Markovich

IPC分类号： H01R12/16

CPC分类号： H05K1/186 ,  H01L23/4985 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/73204 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81385 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2224/92125 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K3/4611 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/10515 ,  H05K2201/10681 ,  Y10T29/49126 ,  Y10T29/49151 ,  H01L2924/00 ,  H01L2224/48 ,  H01L2224/0401

摘要： A circuitized substrate assembly comprised of at least two circuitized substrates each including a thin dielectric layer and a conductive layer with a plurality of conductive members as part thereof, the conductive members of each substrate being electrically coupled to the conductive sites of a semiconductor chip. A dielectric layer is positioned between both substrates and the substrates are bonded together, such that the chips are internally located within the assembly and oriented in a stacked orientation. A method of making such an assembly is also provided, as is an electrical assembly utilizing same and an information handling system adapted for having such an electrical assembly as part thereof.

摘要翻译： 电路化衬底组件由至少两个电路化衬底组成，每个衬底均包括薄介电层和具有多个导电构件作为其一部分的导电层，每个衬底的导电构件电耦合到半导体芯片的导电部位。 电介质层位于两个基板之间，并且基板接合在一起，使得芯片在内部位于组件内并且以堆叠取向定向。 还提供了制造这种组件的方法，以及使用其的电组件以及适于将这种电组件作为其一部分的信息处理系统。

公开(公告)号：US20080217050A1

公开(公告)日：2008-09-11

申请号：US11873435

申请日：2007-10-17

申请人： Frank D. Egitto ,  Donald S. Farquhar ,  Voya R. Markovich ,  Mark D. Poliks ,  Douglas O. Powell

发明人： Frank D. Egitto ,  Donald S. Farquhar ,  Voya R. Markovich ,  Mark D. Poliks ,  Douglas O. Powell

IPC分类号： H01R12/04 ,  B29C65/48

CPC分类号： H01L21/4853 ,  H01L23/3735 ,  H01L23/49822 ,  H01L2224/16225 ,  H01L2924/01004 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01068 ,  H01L2924/01078 ,  H01L2924/01322 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/114 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4608 ,  H05K3/462 ,  H05K3/4623 ,  H05K3/4626 ,  H05K3/4632 ,  H05K3/4641 ,  H05K3/4688 ,  H05K2201/0141 ,  H05K2201/0191 ,  H05K2201/068 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/09554 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/10378 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T156/1092

摘要： A multi-layered interconnect structure and method of formation. In a first embodiment, first and second liquid crystal polymer (LCP) dielectric layers are directly bonded, respectively, to first and second opposing surface of a thermally conductive layer, with no extrinsic adhesive material bonding the thermally conductive layer with either the first or second LCP dielectric layer. In a second embodiment, first and second 2S1P substructures are directly bonded, respectively, to first and second opposing surfaces of a LCP dielectric joining layer, with no extrinsic adhesive material bonding the LCP dielectric joining layer with either the first or second 2S1P substructures.

摘要翻译： 多层互连结构和形成方法。 在第一实施例中，第一和第二液晶聚合物（LCP）电介质层分别直接接合到导热层的第一和第二相对表面，没有外在粘合材料将导热层与第一或第二液晶聚合物 LCP电介质层。 在第二实施例中，第一和第二2S1P子结构分别直接接合到LCP电介质接合层的第一和第二相对表面，没有外部粘合材料将LCP电介质接合层与第一或第二2S1P子结构结合。

公开(公告)号：US20080142258A1

公开(公告)日：2008-06-19

申请号：US12010335

申请日：2008-01-24

申请人： David V, Caletka ,  Frank D. Egitto

发明人： David V, Caletka ,  Frank D. Egitto

IPC分类号： H05K1/11

CPC分类号： H05K1/0219 ,  H01R12/523 ,  H01R13/2414 ,  H05K1/113 ,  H05K3/4046 ,  H05K3/429 ,  H05K3/4614 ,  H05K2201/0959 ,  H05K2201/09809 ,  H05K2201/10303 ,  H05K2201/10378 ,  Y10T29/49155 ,  Y10T29/49165

摘要： A high speed interposer which includes a substrate having alternatingly oriented dielectric and conductive layers which form a substrate, openings which extend from one opposing surface of the substrate to a second opposing surface, conductive members positioned within the openings and also extending from surface to surface (and beyond, in some embodiments), and a plurality of shielding members positioned substantially around the conductive members to provide shielding therefore during the passage of high frequency signals through the conductive members.

摘要翻译： 高速插入器，其包括具有交替取向的介电层和导电层的基板，其形成基板，从基板的一个相对表面延伸到第二相对表面的开口，定位在开口内并且还从表面延伸到表面的导电构件 并且在一些实施例中超越）以及基本上围绕导电构件定位的多个屏蔽构件，从而在高频信号通过导电构件期间提供屏蔽。

公开(公告)号：US20070275525A1

公开(公告)日：2007-11-29

申请号：US11438424

申请日：2006-05-23

申请人： Rabindra N. Das ,  Frank D. Egitto ,  John M. Lauffer ,  How T. Lin ,  Voya R. Markovich

发明人： Rabindra N. Das ,  Frank D. Egitto ,  John M. Lauffer ,  How T. Lin ,  Voya R. Markovich

IPC分类号： H01L21/8242

CPC分类号： H05K1/162 ,  H01L27/12 ,  H01L28/40 ,  H05K1/0306 ,  H05K3/125 ,  H05K3/4667 ,  H05K2201/0187 ,  H05K2201/09509 ,  H05K2203/013

摘要： A capacitive substrate and method of making same in which first and second glass layers are used. A first conductor is formed on a first of the glass layers and a capacitive dielectric material is positioned over the conductor. The second conductor is then positioned on the capacitive dielectric and the second glass layer positioned over the second conductor. Conductive thru-holes are formed to couple to the first and second conductors, respectively, such that the conductors and capacitive dielectric material form a capacitor when the capacitive substrate is in operation.

摘要翻译： 电容性基板及其制造方法，其中使用第一和第二玻璃层。 第一导体形成在第一玻璃层上，并且电容电介质材料位于导体上方。 然后将第二导体定位在电容电介质上，并且第二玻璃层位于第二导体上。 形成导电通孔以分别耦合到第一和第二导体，使得当电容基板工作时，导体和电容电介质材料形成电容器。