公开(公告)号：US09960233B2

公开(公告)日：2018-05-01

申请号：US15600837

申请日：2017-05-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： Siddarth A. Krishnan ,  Unoh Kwon ,  Vijay Narayanan ,  Jeffrey W. Sleight

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/739 ,  H01L29/417 ,  H01L29/423 ,  H01L29/775 ,  H01L29/45 ,  H01L29/165 ,  H01L29/205

CPC classification number: H01L29/0673 ,  H01L29/083 ,  H01L29/165 ,  H01L29/205 ,  H01L29/41758 ,  H01L29/42356 ,  H01L29/45 ,  H01L29/458 ,  H01L29/66356 ,  H01L29/66469 ,  H01L29/66553 ,  H01L29/7391 ,  H01L29/775

Abstract: After forming a buried nanowire segment surrounded by a gate structure located on a substrate, an epitaxial source region is grown on a first end of the buried nanowire segment while covering a second end of the buried nanowire segment and the gate structure followed by growing an epitaxial drain region on the second end of the buried nanowire segment while covering the epitaxial source region and the gate structure. The epitaxial source region includes a first semiconductor material and dopants of a first conductivity type, while the epitaxial drain region includes a first semiconductor material different from the first semiconductor material and dopants of a second conductivity type opposite the first conductivity type.

公开(公告)号：US20160308025A1

公开(公告)日：2016-10-20

申请号：US14685944

申请日：2015-04-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： Michael P. Chudzik ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Vijay Narayanan ,  Jeffrey W. Sleight

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/20 ,  H01L29/88 ,  H01L29/78

CPC classification number: H01L29/66545 ,  H01L21/02538 ,  H01L21/02617 ,  H01L29/0657 ,  H01L29/20 ,  H01L29/267 ,  H01L29/66151 ,  H01L29/66356 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7391 ,  H01L29/785 ,  H01L29/88

Abstract: A semiconductor structure includes a substrate and an intrinsic replacement channel. A tunneling field effect transistor (TFET) fin may be formed by the intrinsic replacement channel, a p-fin and an n-fin formed upon the substrate. The p-fin may serve as the source of the TFET and the n-fin may serve as the drain of the TFET. The replacement channel may be formed in place of a sacrificial channel of a diode fin that includes the p-fin, the n-fin, and the sacrificial channel at the p-fin and n-fin junction.

Abstract translation: 半导体结构包括衬底和固有置换通道。 隧道场效应晶体管（TFET）鳍可以由本征替换沟道，形成在衬底上的p鳍和n鳍形成。 p鳍可以用作TFET的源极，并且n鳍可以用作TFET的漏极。 可以形成替代通道来代替在p鳍和n鳍结上包括p鳍，n鳍和牺牲沟道的二极管鳍片的牺牲通道。

公开(公告)号：US09660027B2

公开(公告)日：2017-05-23

申请号：US14887572

申请日：2015-10-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Siddarth A. Krishnan ,  Unoh Kwon ,  Vijay Narayanan ,  Jeffrey W. Sleight

IPC: H01L29/06 ,  H01L29/41 ,  H01L29/66 ,  H01L29/417 ,  H01L29/423 ,  H01L29/775

CPC classification number: H01L29/0673 ,  H01L29/083 ,  H01L29/165 ,  H01L29/205 ,  H01L29/41758 ,  H01L29/42356 ,  H01L29/45 ,  H01L29/458 ,  H01L29/66356 ,  H01L29/66469 ,  H01L29/66553 ,  H01L29/7391 ,  H01L29/775

Abstract: After forming a buried nanowire segment surrounded by a gate structure located on a substrate, an epitaxial source region is grown on a first end of the buried nanowire segment while covering a second end of the buried nanowire segment and the gate structure followed by growing an epitaxial drain region on the second end of the buried nanowire segment while covering the epitaxial source region and the gate structure. The epitaxial source region includes a first semiconductor material and dopants of a first conductivity type, while the epitaxial drain region includes a first semiconductor material different from the first semiconductor material and dopants of a second conductivity type opposite the first conductivity type.

公开(公告)号：US20170263707A1

公开(公告)日：2017-09-14

申请号：US15600837

申请日：2017-05-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： Siddarth A. Krishnan ,  Unoh Kwon ,  Vijay Narayanan ,  Jeffrey W. Sleight

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/417

CPC classification number: H01L29/0673 ,  H01L29/083 ,  H01L29/165 ,  H01L29/205 ,  H01L29/41758 ,  H01L29/42356 ,  H01L29/45 ,  H01L29/458 ,  H01L29/66356 ,  H01L29/66469 ,  H01L29/66553 ,  H01L29/7391 ,  H01L29/775

Abstract: After forming a buried nanowire segment surrounded by a gate structure located on a substrate, an epitaxial source region is grown on a first end of the buried nanowire segment while covering a second end of the buried nanowire segment and the gate structure followed by growing an epitaxial drain region on the second end of the buried nanowire segment while covering the epitaxial source region and the gate structure. The epitaxial source region includes a first semiconductor material and dopants of a first conductivity type, while the epitaxial drain region includes a first semiconductor material different from the first semiconductor material and dopants of a second conductivity type opposite the first conductivity type.

公开(公告)号：US20170110539A1

公开(公告)日：2017-04-20

申请号：US14887572

申请日：2015-10-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Siddarth A. Krishnan ,  Unoh Kwon ,  Vijay Narayanan ,  Jeffrey W. Sleight

IPC: H01L29/06 ,  H01L29/775 ,  H01L29/66 ,  H01L29/417 ,  H01L29/423

CPC classification number: H01L29/0673 ,  H01L29/083 ,  H01L29/165 ,  H01L29/205 ,  H01L29/41758 ,  H01L29/42356 ,  H01L29/45 ,  H01L29/458 ,  H01L29/66356 ,  H01L29/66469 ,  H01L29/66553 ,  H01L29/7391 ,  H01L29/775

Abstract: After forming a buried nanowire segment surrounded by a gate structure located on a substrate, an epitaxial source region is grown on a first end of the buried nanowire segment while covering a second end of the buried nanowire segment and the gate structure followed by growing an epitaxial drain region on the second end of the buried nanowire segment while covering the epitaxial source region and the gate structure. The epitaxial source region includes a first semiconductor material and dopants of a first conductivity type, while the epitaxial drain region includes a first semiconductor material different from the first semiconductor material and dopants of a second conductivity type opposite the first conductivity type.

公开(公告)号：US09530860B2

公开(公告)日：2016-12-27

申请号：US14578768

申请日：2014-12-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： Pranita Kerber ,  Chung-Hsun Lin ,  Amlan Majumdar ,  Jeffrey W. Sleight

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/66522 ,  H01L29/1083 ,  H01L29/205 ,  H01L29/66492 ,  H01L29/66537 ,  H01L29/66575 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7834

Abstract: Techniques for controlling short channel effects in III-V MOSFETs through the use of a halo-doped bottom (III-V) barrier layer are provided. In one aspect, a method of forming a MOSFET device is provided. The method includes the steps of: forming a III-V barrier layer on a substrate; forming a III-V channel layer on a side of the III-V barrier layer opposite the substrate, wherein the III-V barrier layer is configured to confine charge carriers in the MOSFET device to the III-V channel layer; forming a gate stack on a side of the III-V channel layer opposite the III-V barrier layer; and forming halo implants in the III-V barrier layer on opposite sides of the gate stack. A MOSFET device is also provided.

Abstract translation: 提供了通过使用卤素掺杂的底部（III-V）阻挡层来控制III-V MOSFET中的短沟道效应的技术。 在一个方面，提供了一种形成MOSFET器件的方法。 该方法包括以下步骤：在衬底上形成III-V阻挡层; 在与衬底相对的III-V阻挡层的一侧上形成III-V沟道层，其中III-V势垒层被配置为将MOSFET器件中的电荷载流子限制到III-V沟道层; 在与III-V阻挡层相对的III-V沟道层的一侧上形成栅叠层; 以及在栅堆叠的相对侧上的III-V阻挡层中形成晕轮植入物。 还提供MOSFET器件。

公开(公告)号：US09437443B2

公开(公告)日：2016-09-06

申请号：US13916109

申请日：2013-06-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： Markus Brink ,  Michael A. Guillorn ,  Sebastian U. Engelmann ,  Hiroyuki Miyazoe ,  Adam M. Pyzyna ,  Jeffrey W. Sleight

IPC: H01L21/308 ,  H01L21/033 ,  H01L21/02 ,  H01L21/3213 ,  H01L21/28

CPC classification number: H01L21/3086 ,  H01L21/0228 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/28132 ,  H01L21/3088 ,  H01L21/32139

Abstract: A SIT method includes the following steps. An SIT mandrel material is deposited onto a substrate and formed into a plurality of SIT mandrels. A spacer material is conformally deposited onto the substrate covering a top and sides of each of the SIT mandrels. Atomic Layer Deposition (ALD) is used to deposit the SIT spacer at low temperatures. The spacer material is selected from the group including a metal, a metal oxide, a metal nitride and combinations including at least one of the foregoing materials. The spacer material is removed from all but the sides of each of the SIT mandrels to form SIT sidewall spacers on the sides of each of the SIT mandrels. The SIT mandrels are removed selective to the SIT sidewall spacers revealing a pattern of the SIT sidewall spacers. The pattern of the SIT sidewall spacers is transferred to the underlying stack or substrate.

Abstract translation: SIT方法包括以下步骤。 将SIT芯棒材料沉积到衬底上并形成多个SIT芯棒。 间隔物材料被共形沉积到基底上，覆盖每个SIT心轴的顶部和侧面。 原子层沉积（ALD）用于在低温下沉积SIT间隔物。 间隔材料选自金属，金属氧化物，金属氮化物和包括至少一种前述材料的组合。 隔离材料从每个SIT心轴的所有侧面除去，以在每个SIT心轴的侧面上形成SIT侧壁间隔物。 SIT心轴被选择性地移除到SIT侧壁间隔件上，露出SIT侧壁间隔物的图案。 SIT侧壁间隔物的图案被转移到下面的堆叠或衬底。

公开(公告)号：US20160099329A1

公开(公告)日：2016-04-07

申请号：US14968061

申请日：2015-12-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： Anirban Basu ,  Guy Cohen ,  Amlan Majumdar ,  Jeffrey W. Sleight

IPC: H01L29/423 ,  H01L21/31 ,  H01L21/306 ,  H01L21/768 ,  H01L21/265 ,  H01L21/3105 ,  H01L29/417 ,  H01L29/66 ,  H01L21/283

CPC classification number: H01L29/42392 ,  H01L21/265 ,  H01L21/283 ,  H01L21/30604 ,  H01L21/31 ,  H01L21/31055 ,  H01L21/76802 ,  H01L21/76879 ,  H01L29/41733 ,  H01L29/41783 ,  H01L29/66545 ,  H01L29/66666 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78696

Abstract: A semiconductor fin including a vertical stack, from bottom to top, of a second semiconductor material and a first semiconductor material is formed on a substrate. A disposable gate structure straddling the semiconductor fin is formed. A source region and a drain region are formed employing the disposable gate structure as an implantation mask, At least one semiconductor shell layer or a semiconductor cap layer can be formed as an etch stop structure. A planarization dielectric layer is subsequently formed. A gate cavity is formed by removing the disposable gate structure. A portion of the second semiconductor material is removed selective to the first semiconductor material within the gate cavity so that a middle portion of the semiconductor fin becomes suspended over the substrate. A gate dielectric layer and a gate electrode are sequentially formed. The gate electrode laterally surrounds a body region of a fin field effect transistor.

公开(公告)号：US09209086B2

公开(公告)日：2015-12-08

申请号：US13947316

申请日：2013-07-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Josephine B. Chang ,  Michael A. Guillorn ,  Gen P. Lauer ,  Isaac Lauer ,  Jeffrey W. Sleight

IPC: H01L21/8234 ,  H01L29/66 ,  H01L29/78 ,  H01L21/84 ,  H01L29/06 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/775

CPC classification number: H01L21/823431 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/845 ,  H01L29/0665 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/41775 ,  H01L29/66439 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/78 ,  H01L29/785

Abstract: Techniques for integrating low temperature salicide formation in a replacement gate device process flow are provided. In one aspect, a method of fabricating a FET device is provided that includes the following steps. A dummy gate(s) is formed over an active area of a wafer. A gap filler material is deposited around the dummy gate. The dummy gate is removed selective to the gap filler material, forming a trench in the gap filler material. A replacement gate is formed in the trench in the gap filler material. The replacement gate is recessed below a surface of the gap filler material. A gate cap is formed in the recess above the replacement gate. The gap filler material is etched back to expose at least a portion of the source and drain regions of the device. A salicide is formed on source and drain regions of the device.

Abstract translation: 提供了在替代浇口装置工艺流程中集成低温自对准硅化物形成技术。 一方面，提供了一种制造FET器件的方法，包括以下步骤。 在晶片的有效区域上形成虚拟栅极。 间隙填充材料沉积在虚拟栅极周围。 虚拟栅极被选择性地移除到间隙填充材料上，在间隙填充材料中形成沟槽。 在间隙填充材料的沟槽中形成替换栅极。 更换浇口凹陷在间隙填充材料的表面下方。 在替换门上方的凹槽中形成栅极盖。 间隙填充材料被回蚀以暴露该器件的源极和漏极区域的至少一部分。 在设备的源极和漏极区域上形成自对准硅化物。

公开(公告)号：US09627508B2

公开(公告)日：2017-04-18

申请号：US14685944

申请日：2015-04-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： Michael P. Chudzik ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Vijay Narayanan ,  Jeffrey W. Sleight

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/88 ,  H01L29/20 ,  H01L21/02 ,  H01L29/739 ,  H01L29/267

CPC classification number: H01L29/66545 ,  H01L21/02538 ,  H01L21/02617 ,  H01L29/0657 ,  H01L29/20 ,  H01L29/267 ,  H01L29/66151 ,  H01L29/66356 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7391 ,  H01L29/785 ,  H01L29/88

Abstract: A semiconductor structure includes a substrate and an intrinsic replacement channel. A tunneling field effect transistor (TFET) fin may be formed by the intrinsic replacement channel, a p-fin and an n-fin formed upon the substrate. The p-fin may serve as the source of the TFET and the n-fin may serve as the drain of the TFET. The replacement channel may be formed in place of a sacrificial channel of a diode fin that includes the p-fin, the n-fin, and the sacrificial channel at the p-fin and n-fin junction.