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    GATE STRUCTURES
    6.
    发明申请
    GATE STRUCTURES 审中-公开

    公开(公告)号：US20200161136A1

    公开(公告)日：2020-05-21

    申请号：US16193960

    申请日：2018-11-16

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Jiehui SHU ,  Hui ZANG

    IPC: H01L21/28 ,  H01L23/535 ,  H01L27/088 ,  H01L29/49 ,  H01L29/66 ,  H01L21/8234

    Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to gate structures and methods of manufacture. The structure includes: a plurality of gate structures comprising a gate cap, sidewall spacers and source and drain regions; source and drain metallization features extending to the source and drain regions; and a liner extending along an upper portion of the sidewall spacers of at least one of the plurality of gate structures.

    REDUCED SILICON GOUGING DURING OXIDE SPACER FORMATION
    7.
    发明申请
    REDUCED SILICON GOUGING DURING OXIDE SPACER FORMATION 审中-公开
    在氧化物间隙形成期间减少硅胶

    公开(公告)号：US20150325445A1

    公开(公告)日：2015-11-12

    申请号：US14270995

    申请日：2014-05-06

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Jiehui SHU ,  Huang LIU

    IPC: H01L21/28 ,  H01L21/311 ,  H01L29/40

    CPC classification number: H01L29/6656 ,  H01L21/28035 ,  H01L21/28238 ,  H01L21/31116 ,  H01L29/401

    Abstract: An improved method for fabricating a semiconductor device is provided to decrease substrate gouging during oxide spacer formation. The method includes: forming a gate structure on a substrate; depositing an oxide layer along the sidewalls of the gate structure and on the substrate; removing some of the oxide layer to define oxide spacers along sidewalls of the gate structure; and performing an isotropic etch process to remove a residual portion of the oxide layer.

    Abstract translation: 提供了一种用于制造半导体器件的改进方法，用于在氧化物间隔物形成期间减少衬底气刨。 该方法包括：在基板上形成栅极结构; 沿着栅极结构的侧壁和衬底上沉积氧化物层; 去除所述氧化物层中的一些以在所述栅极结构的侧壁上限定氧化物间隔物; 并执行各向同性蚀刻工艺以除去氧化物层的残留部分。

    MIDDLE OF LINE GATE STRUCTURES
    8.
    发明申请
    MIDDLE OF LINE GATE STRUCTURES 审中-公开

    公开(公告)号：US20200335619A1

    公开(公告)日：2020-10-22

    申请号：US16386902

    申请日：2019-04-17

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Yanping SHEN ,  Haiting WANG ,  Hui ZANG ,  Jiehui SHU

    IPC: H01L29/78 ,  H01L21/8238 ,  H01L21/8234 ,  H01L29/66

    Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to middle of line gate structures and methods of manufacture. The structure includes: a plurality of adjacent gate structures; a bridged gate structure composed of a plurality of the adjacent gate structures; source and drain regions adjacent to the bridged gate structure and comprising source and drain metallization features; and contacts to the bridged gate structure and the source and drain metallization features.

    SEMICONDUCTOR STRUCTURE
    9.
    发明申请
    SEMICONDUCTOR STRUCTURE 审中-公开

    公开(公告)号：US20180350607A1

    公开(公告)日：2018-12-06

    申请号：US15611231

    申请日：2017-06-01

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Jiehui SHU ,  Haifeng SHENG ,  Jinping LIU

    IPC: H01L21/28 ,  H01L21/02 ,  H01L21/768 ,  H01L21/311

    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to methods to remove a contact etch stop layer without consuming material of a self-aligned contact (SAC) layer. The method includes: forming a gate structure on a substrate; forming a capping layer on the gate structure; forming a contact etch stop layer of a first material, adjacent to the gate metal structure; converting the contact etch stop layer to a second material which is different than the capping layer; and selectively removing the second material without completely removing the capping layer.

    DEVICES AND METHODS OF FORMING SADP ON SRAM AND SAQP ON LOGIC
    10.
    发明申请
    DEVICES AND METHODS OF FORMING SADP ON SRAM AND SAQP ON LOGIC 审中-公开

    公开(公告)号：US20180012760A1

    公开(公告)日：2018-01-11

    申请号：US15674763

    申请日：2017-08-11

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Jiehui SHU ,  Daniel JAEGER ,  Garo Jacques DERDERIAN ,  Haifeng SHENG ,  Jinping LIU

    IPC: H01L21/033 ,  H01L27/11

    CPC classification number: H01L27/1116 ,  H01L21/3086 ,  H01L27/1104 ,  H01L28/00

    Abstract: Devices and methods of fabricating integrated circuit devices with reduced cell height are provided. One method includes, for instance: obtaining an intermediate semiconductor device having a substrate including a logic area and an SRAM area, a fin material layer, and a hardmask layer; depositing a mandrel over the logic area; depositing a sacrificial spacer layer; etching the sacrificial spacer layer to define a sacrificial set of vertical spacers; etching the hardmask layer; leaving a set of vertical hardmask spacers; depositing a first spacer layer; etching the first spacer layer to define a first set of vertical spacers over the logic area; depositing an SOH layer; etching an opening in the SOH layer over the SRAM area; depositing a second spacer layer; and etching the second spacer layer to define a second set of spacers over the SRAM area.

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