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    Asymmetric stressor DRAM
    4.
    发明授权
    Asymmetric stressor DRAM 有权
    不对称应力源DRAM

    公开(公告)号：US09240482B2

    公开(公告)日：2016-01-19

    申请号：US14476897

    申请日：2014-09-04

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Ravi K. Dasaka ,  Shreesh Narasimha ,  Ahmed Nayaz Noemaun ,  Karen A. Nummy ,  Katsunori Onishi ,  Paul C. Parries ,  Chengwen Pei ,  Geng Wang ,  Bidan Zhang

    IPC: H01L21/00 ,  H01L29/78 ,  H01L27/108

    CPC classification number: H01L29/7848 ,  H01L21/84 ,  H01L27/10829 ,  H01L27/10832 ,  H01L27/10867 ,  H01L27/10873 ,  H01L27/10894 ,  H01L27/1203 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66636 ,  H01L29/66659

    Abstract: A stressor structure is formed within a drain region of an access transistor in a dynamic random access memory (DRAM) cell in a semiconductor-on-insulator (SOI) substrate without forming any stressor structure in a source region of the DRAM cell. The stressor structure induces a stress gradient within the body region of the access transistor, which induces a greater leakage current at the body-drain junction than at the body-source junction. The body potential of the access transistor has a stronger coupling to the drain voltage than to the source voltage. An asymmetric etch of a gate dielectric cap, application of a planarization material layer, and a non-selective etch of the planarization material layer and the gate dielectric cap can be employed to form the DRAM cell.

    Abstract translation: 在绝缘体上半导体（SOI）衬底中的动态随机存取存储器（DRAM）单元中的存取晶体管的漏极区域内形成应力器结构，而不在DRAM单元的源极区域中形成任何应力结构。 应力器结构在存取晶体管的体区内引起应力梯度，其在体 - 漏接点处比在体 - 源结处引起更大的漏电流。 存取晶体管的体电位与漏极电压的耦合比源电压更强。 栅极电介质盖的非对称蚀刻，平坦化材料层的施加以及平坦化材料层和栅极电介质盖的非选择性蚀刻可用于形成DRAM单元。

    LOW ENERGY ION IMPLANTATION OF A JUNCTION BUTTING REGION
    5.
    发明申请
    LOW ENERGY ION IMPLANTATION OF A JUNCTION BUTTING REGION 审中-公开
    一个连接区域的低能量离子植入

    公开(公告)号：US20150348974A1

    公开(公告)日：2015-12-03

    申请号：US14820667

    申请日：2015-08-07

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Shreesh Narasimha ,  Katsunori Onishi ,  Paul C. Parries ,  Chengwen Pei ,  Geng Wang

    IPC: H01L27/108 ,  H01L29/06

    CPC classification number: H01L27/10802 ,  H01L21/84 ,  H01L27/10891 ,  H01L27/1203 ,  H01L29/0603 ,  H01L29/0646 ,  H01L29/66636 ,  H01L29/78

    Abstract: The present invention relates generally to semiconductor devices and more particularly, to a structure and method of forming a junction butting region using low energy ion implantation to reduce parasitic leakage and body-to-body leakage between adjacent FETs that share a common contact in high density memory technologies, such as dynamic random access memory (DRAM) devices and embedded DRAM (eDRAM) devices. A method disclosed may include forming a junction butting region at the bottom of a trench formed in a semiconductor on insulator (SOI) layer using low energy ion implantation and protecting adjacent structures from damage from ion scattering using a protective layer.

    Abstract translation: 本发明一般涉及半导体器件，更具体地，涉及使用低能离子注入形成结对接区域以减少高密度共享公共接触的相邻FET之间的寄生泄漏和体对体泄漏的结构和方法 存储器技术，例如动态随机存取存储器（DRAM）器件和嵌入式DRAM（eDRAM）器件。 所公开的方法可以包括在使用低能离子注入的半导体绝缘体（SOI）层上形成的沟槽的底部形成接合对接区域，并使用保护层保护相邻结构免受离子散射的损害。

    FORMING INTERCONNECT WITHOUT GATE CUT ISOLATION BLOCKING OPENING FORMATION
    7.
    发明申请
    FORMING INTERCONNECT WITHOUT GATE CUT ISOLATION BLOCKING OPENING FORMATION 有权

    公开(公告)号：US20210028067A1

    公开(公告)日：2021-01-28

    申请号：US16517827

    申请日：2019-07-22

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Daniel J. Jaeger ,  Naved A. Siddiqui ,  Shimpei Yamaguchi ,  Shreesh Narasimha

    IPC: H01L21/8234 ,  H01L21/768 ,  H01L27/088 ,  H01L29/66 ,  H01L29/78

    Abstract: A method includes forming a gate cut opening by removing a sacrificial material from a portion of a dummy gate in a first dielectric over a substrate. The gate cut opening includes a lower portion in which the sacrificial material was located and an upper portion extending laterally over the first dielectric. Filling the gate cut opening with a second dielectric creates a gate cut isolation. Recessing the second dielectric creates a cap opening in the second dielectric; and filling the cap opening with a third dielectric creates a dielectric cap. The third dielectric is different than the second dielectric, e.g., oxide versus nitride, allowing forming of an interconnect in at least a portion of the third dielectric without the second, harder dielectric acting as an etch stop.

    Silicon nitride layer deposited at low temperature to prevent gate dielectric regrowth high-K metal gate field effect transistors
    9.
    发明授权
    Silicon nitride layer deposited at low temperature to prevent gate dielectric regrowth high-K metal gate field effect transistors 有权
    在低温下沉积氮化硅层，以防止栅介质再生长高K金属栅场效应晶体管

    公开(公告)号：US09269786B2

    公开(公告)日：2016-02-23

    申请号：US14037423

    申请日：2013-09-26

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Anthony I-Chih Chou ,  Arvind Kumar ,  Shreesh Narasimha ,  Claude Ortolland ,  Kai Zhao

    IPC: H01L29/76 ,  H01L29/51 ,  H01L27/092 ,  H01L21/8238

    CPC classification number: H01L29/518 ,  H01L21/28176 ,  H01L21/823821 ,  H01L21/823842 ,  H01L27/0924 ,  H01L29/511 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/78

    Abstract: Standard High-K metal gate (HKMG) CMOS technologies fabricated using the replacement metal gate (RMG), also known as gate-last, integration flow, are susceptible to oxygen ingress into the high-K gate dielectric layer and oxygen diffusion into the gate dielectric and semiconductor channel region. The oxygen at the gate dielectric and semiconductor channel interface induces unwanted oxide regrowth that results in an effective oxide thickness increase, and transistor threshold voltage shifts, both of which are highly variable and degrade semiconductor chip performance. By introducing silicon nitride deposited at low temperature, after the metal gate formation, the oxygen ingress and gate dielectric regrowth can be avoided, and a high semiconductor chip performance is maintained.

    Abstract translation: 使用替代金属栅极（RMG）制造的标准高K金属栅极（HKMG）CMOS技术也被称为最终集成流，易受氧进入高K栅介质层和氧气扩散入栅极 电介质和半导体沟道区。 栅极电介质和半导体沟道界面处的氧会引起不必要的氧化物再生长，导致有效的氧化物厚度增加，并且晶体管阈值电压偏移，这两者都是高度可变的并且降低半导体芯片性能。 通过引入在低温下沉积的氮化硅，在金属栅极形成之后，可以避免氧进入和栅介质再生长，并且保持高的半导体芯片性能。

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