公开(公告)号：US10192822B2

公开(公告)日：2019-01-29

申请号：US14623115

申请日：2015-02-16

Applicant: GLOBALFOUNDRIES INC.

Inventor： Domingo A. Ferrer ,  Kriteshwar K. Kohli ,  Siddarth A. Krishnan ,  Joseph F. Shepard, Jr. ,  Keith Kwong Hon Wong

IPC: H01L27/112 ,  H01L23/525 ,  H01L23/522 ,  H01L21/768

Abstract: A method for forming a precision resistor or an e-fuse structure where tungsten silicon is used. The tungsten silicon layer is modified by implanting nitrogen into the structure.

公开(公告)号：US10355104B2

公开(公告)日：2019-07-16

申请号：US15795833

申请日：2017-10-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yi Qi ,  Sang Woo Lim ,  Kyung-Bum Koo ,  Alina Vinslava ,  Pei Zhao ,  Zhenyu Hu ,  Hsien-Ching Lo ,  Joseph F. Shepard, Jr. ,  Shesh Mani Pandey

IPC: H01L21/02 ,  H01L21/84 ,  H01L29/66 ,  H01L21/3065 ,  H01L29/78 ,  H01L29/161 ,  H01L29/16 ,  H01L29/165 ,  H01L29/08

Abstract: Methods of forming a field-effect transistor and structures for a field-effect transistor. A gate structure is formed that overlaps with a channel region beneath a top surface of a semiconductor fin. The semiconductor fin is etched with an anisotropic etching process to form a cavity having a sidewall with a planar section extending vertically toward the top surface of the semiconductor fin and adjacent to the channel region in the semiconductor fin. The semiconductor fin is then etched with an isotropic etching process that widens the cavity at the top surface while preserving verticality of the planar section.

公开(公告)号：US09806161B1

公开(公告)日：2017-10-31

申请号：US15092910

申请日：2016-04-07

Applicant: GLOBALFOUNDRIES INC.

Inventor： Shahrukh A. Khan ,  Unoh Kwon ,  Shahab Siddiqui ,  Sean M. Polvino ,  Joseph F. Shepard, Jr.

IPC: H01L29/423 ,  H01L21/311 ,  H01L29/51 ,  H01L21/033 ,  H01L21/84 ,  H01L21/027 ,  H01L21/8234 ,  H01L27/12

CPC classification number: H01L29/42364 ,  H01L21/0273 ,  H01L21/0332 ,  H01L21/28202 ,  H01L21/31133 ,  H01L21/31144 ,  H01L21/823431 ,  H01L21/823462 ,  H01L21/845 ,  H01L27/1207 ,  H01L29/511 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66545

Abstract: One aspect of the disclosure relates to and integrated circuit structure and methods of forming the same. The integrated circuit structure may include: a thin gate dielectric device on a substrate, the thin gate dielectric device including: a first interfacial layer over a set of fins within the substrate, wherein the interfacial layer has a thickness of approximately 1.0 nanometers (nm) to approximately 1.2 nm; and a thick gate dielectric device on the substrate adjacent to the thin gate dielectric device, the thick gate dielectric device including: a second interfacial layer over the set of fins within the substrate; and a nitrided oxide layer over the second interfacial layer, wherein the nitrided oxide layer includes a thickness of approximately 3.5 nm to approximately 5.0 nm.

公开(公告)号：US09257519B2

公开(公告)日：2016-02-09

申请号：US14081417

申请日：2013-11-15

Applicant: GLOBALFOUNDRIES INC.

Inventor： Michael P. Chudzik ,  Min Dai ,  Jinping Liu ,  Joseph F. Shepard, Jr. ,  Keith K. H. Wong

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/336 ,  H01L29/49 ,  H01L29/47 ,  H01L21/28 ,  H01L29/51

CPC classification number: H01L29/4966 ,  H01L21/28202 ,  H01L29/47 ,  H01L29/51 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

Abstract: A semiconductor device is disclosed. The semiconductor device includes a substrate; and a gate structure disposed directly on the substrate, the gate structure including: a graded region with a varied material concentration profile; and a metal layer disposed on the graded region.

Abstract translation: 公开了一种半导体器件。 半导体器件包括衬底; 以及栅极结构，其直接设置在所述基板上，所述栅极结构包括：具有不同材料浓度分布的渐变区域; 以及设置在分级区域上的金属层。

公开(公告)号：US10211045B1

公开(公告)日：2019-02-19

申请号：US15878502

申请日：2018-01-24

Applicant: GLOBALFOUNDRIES INC.

Inventor： Rishikesh Krishnan ,  Joseph K. Kassim ,  Bharat V. Krishnan ,  Joseph F. Shepard, Jr. ,  Rinus Tek Po Lee ,  Yiheng Xu

IPC: H01L21/02 ,  H01L21/3105 ,  H01L29/06 ,  H01L21/762 ,  H01L27/088

Abstract: An insulator is formed by flowable chemical vapor deposition (FCVD) process. The insulator is cured by exposing the insulator to ultraviolet light while flowing ozone over the insulator to produce a cured insulator. The curing process forms nitrogen, hydrogen, nitrogen monohydride, or hydroxyl-rich atomic clusters in the insulator. Following the curing process, these methods select wavelengths of microwave radiation (that will be subsequently used during annealing) so that such wavelengths excite the nitrogen, hydrogen, nitrogen monohydride, or hydroxyl-rich atomic clusters. Then, these methods anneal the cured insulator by exposing the cured insulator to microwave radiation in an inert (e.g., non-oxidizing) ambient atmosphere, at a temperature below 500° C., so as to increase the density of the cured insulator.

公开(公告)号：US10043753B2

公开(公告)日：2018-08-07

申请号：US15377592

申请日：2016-12-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Huy Cao ,  Zhiguo Sun ,  Joseph F. Shepard, Jr. ,  Moosung M. Chae

IPC: H01L23/522 ,  H01L21/768 ,  H01L21/764 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L23/5283 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02216 ,  H01L21/02271 ,  H01L21/76802 ,  H01L21/7682 ,  H01L21/76831 ,  H01L21/76837 ,  H01L23/5222 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to airgaps which isolate metal lines and methods of manufacture. The structure includes: a plurality of metal lines formed on an insulator layer; and a dielectric material completely filling a space having a first dimension between metal lines of the plurality of metal lines and providing a uniform airgap with a space having a second dimension between metal lines of the plurality of metal lines. The first dimension is larger than the second dimension.

公开(公告)号：US09059315B2

公开(公告)日：2015-06-16

申请号：US13732455

申请日：2013-01-02

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

Inventor： Takashi Ando ,  Maryjane Brodsky ,  Michael P. Chudzik ,  Min Dai ,  Siddarth A. Krishnan ,  Joseph F. Shepard, Jr. ,  Yanfeng Wang ,  Jinping Liu

IPC: H01L21/3205 ,  H01L21/4763 ,  H01L21/8238

CPC classification number: H01L21/823857

Abstract: Embodiments include methods of forming an nFET-tuned gate dielectric and a pFET-tuned gate dielectric. Methods may include forming a high-k layer above a substrate having a pFET region and an nFET region, forming a first sacrificial layer, a pFET work-function metal layer, and a second sacrificial layer above the first high-k layer in the pFET region, and an nFET work-function metal layer above the first high-k layer in the nFET region and above the second sacrificial layer in the pFET region. The first high-k layer then may be annealed to form an nFET gate dielectric layer in the nFET region and a pFET gate dielectric layer in the pFET region. The first high-k layer may be annealed in the presence of a nitrogen source to cause atoms from the nitrogen source to diffuse into the first high-k layer in the nFET region.

Abstract translation: 实施例包括形成nFET调谐的栅极电介质和pFET调谐的栅极电介质的方法。 方法可以包括在pFET区域和nFET区域之上形成高k层，形成第一牺牲层，pFET功函数金属层和在pFET中的第一高k层上方的第二牺牲层 区域，以及在nFET区域中的第一高k层上方的nFET功函数金属层，并且在pFET区域中的第二牺牲层上方。 第一高k层然后可以退火以在nFET区域中形成nFET栅极介电层，并在pFET区域中形成pFET栅极电介质层。 第一高k层可以在存在氮源的情况下进行退火，以使来自氮源的原子扩散到nFET区域中的第一高k层。