公开(公告)号：US20240036470A1

公开(公告)日：2024-02-01

申请号：US18356700

申请日：2023-07-21

Applicant: IMEC VZW

Inventor： Waikin Li ,  Zheng Tao

IPC: G03F7/11 ,  G03F7/00 ,  G03F1/38 ,  G03F1/56 ,  G03F7/09

CPC classification number: G03F7/11 ,  G03F7/0035 ,  G03F1/38 ,  G03F1/56 ,  G03F7/094

Abstract: A method is provided for forming an interconnect structure for an integrated circuit. The method includes: forming a metal layer over a substrate; forming a hard mask layer over the metal layer; forming a first resist layer of a first resist material over the hard mask layer and patterning the first resist layer in a first lithography process to define a first resist pattern; forming over the first resist pattern a second resist layer of a second resist material different from the first resist material and patterning the second resist layer in a second lithography process to define a second resist pattern of resist lines extending in parallel along a first direction, wherein at least a portion of the first resist pattern is overlapped by the second resist pattern; patterning the hard mask layer using the second resist pattern as an etch mask to define a hard mask line pattern underneath the second resist pattern, and subsequently the metal layer to define a metal line pattern underneath the hard mask line pattern; removing the second resist pattern and subsequently patterning the hard mask line pattern using said at least a portion of the first resist pattern as an etch mask to define a hard mask pillar pattern over the metal line pattern; and forming a metal pillar pattern in accordance with the hard mask pillar pattern.

公开(公告)号：US11107812B2

公开(公告)日：2021-08-31

申请号：US16696935

申请日：2019-11-26

Applicant: IMEC vzw

Inventor： Boon Teik Chan ,  Zheng Tao ,  Steven Demuynck

IPC: H01L21/00 ,  H01L27/00 ,  H01L29/00 ,  H01L27/092 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: The disclosed technology relates to a method of forming a stacked semiconductor device. One aspect includes fin structures formed by upper and lower channel layers which are separated by an intermediate layer. After preliminary fun cuts are formed in the fin structure, a sacrificial spacer is formed that covers end surfaces of an upper channel layer portion. Final fin cuts are formed in the fin structure where the lower channel layer is etched which defines a lower channel layer portion. Lower source/drain regions are formed on end surfaces of the lower channel layer portion. The sacrificial spacer shields the end surfaces of the upper channel layer portion allowing for selective deposition of material for the lower source/drain regions.

公开(公告)号：US10153341B2

公开(公告)日：2018-12-11

申请号：US15822275

申请日：2017-11-27

Applicant: IMEC VZW

Inventor： Zheng Tao ,  Boon Teik Chan ,  Soon Aik Chew

IPC: H01L29/06 ,  H01L21/3065 ,  H01L29/66 ,  H01L29/423 ,  H01L29/08 ,  H01L21/02 ,  B82Y10/00

Abstract: A method of forming a semiconductor device comprising horizontal nanowires is described. An example method involves providing a semiconductor structure comprising at least one fin, where the fin includes an alternating stack of layers of sacrificial material and nanowire material, and where the semiconductor structure includes a dummy gate partly covering the stack of layers. The method further involves at least partly removing the sacrificial material, in between the layers of nanowire material, next to the dummy gate thereby forming a void. Still further, the method involves providing spacer material within the void thereby forming an internal spacer. Yet still further the method involves removing the dummy gate, and selectively removing the sacrificial material in that part of the fin which was covered by the dummy gate, thereby releasing the nanowires. The internal spacer is provided before removing the dummy gate and the sacrificial material to release the nanowires.

公开(公告)号：US09548208B2

公开(公告)日：2017-01-17

申请号：US15045923

申请日：2016-02-17

Applicant: IMEC VZW

Inventor： Boon Teik Chan ,  Zheng Tao ,  Nadia Vandenbroeck ,  Safak Sayan

IPC: H01L21/311 ,  H01L21/308 ,  H01L21/033 ,  H01L29/66

CPC classification number: H01L21/3081 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3086 ,  H01L29/66795

Abstract: A method for patterning an underlying layer is described, the method comprising providing a guiding layer on the underlying layer, the guiding layer comprising guiding structures and being substantially planar; providing a block-copolymer layer on the guiding layer; inducing phase separation of the block-copolymer layer in a regular pattern of structures of a first and a second polymer component, whereby one of the components aligns to the guiding structures, by chemo-epitaxy; thereafter, removing a first of the components of the block-copolymer layers completely, leaving a regular pattern of structures of the second component; providing a planarizing layer over the regular pattern of structures of the second component and the guiding layer; removing a portion of the planarizing layer, thereby leaving a regular pattern of structures of the planarizing layer at positions in between the structures of the second component, and exposing the structures of the second component; removing the structures of the second component, selectively with respect to the structures of the planarizing layer; and patterning the underlying layer, thereby using the structures of the planarizing layer as a mask.

Abstract translation: 描述了用于图案化下层的方法，所述方法包括在下层上提供引导层，所述引导层包括引导结构并且基本上是平面的; 在引导层上提供嵌段共聚物层; 诱导嵌段共聚物层以第一和第二聚合物组分的规则形式的结构相分离，由此其中一种组分通过化学外延对准引导结构; 此后，完全去除嵌段共聚物层中的第一组分，留下第二组分的规则的结构图案; 在所述第二部件和所述引导层的结构的规则图案上提供平坦化层; 去除所述平坦化层的一部分，从而在所述第二部件的结构之间的位置处留下所述平坦化层的规则的结构图案，并暴露所述第二部件的结构; 相对于平坦化层的结构选择性地去除第二部件的结构; 并对底层进行图案化，由此使用平坦化层的结构作为掩模。

公开(公告)号：US20240154006A1

公开(公告)日：2024-05-09

申请号：US18501331

申请日：2023-11-03

Applicant: IMEC VZW

Inventor： Zheng Tao ,  Boon Teik Chan

IPC: H01L29/40 ,  H01L29/417

CPC classification number: H01L29/401 ,  H01L29/41733 ,  H01L29/41791 ,  H01L23/535

Abstract: The disclosure relates to a method for forming a semiconductor device. The method includes: forming a device structure on a substrate, the device structure including a fin structure including a pair of source/drain bodies and a channel region between the pair of source/drain bodies, the channel region including at least one channel layer, and the device structure further including a gate structure extending across the channel region of the fin structure. The method also includes forming a metal layer over the source/drain bodies, etching the metal layer to define respective source/drain contacts on the source/drain bodies, and depositing an interlayer dielectric layer over the gate structure and the source/drain contacts.

公开(公告)号：US11776841B2

公开(公告)日：2023-10-03

申请号：US17459384

申请日：2021-08-27

Applicant: IMEC VZW

Inventor： Zheng Tao

IPC: H01L21/74 ,  H01L21/84 ,  H01L23/522 ,  H01L23/535

CPC classification number: H01L21/743 ,  H01L21/845 ,  H01L23/5226 ,  H01L23/535

Abstract: A method is provided for forming a semiconductor product including providing a substrate comprising a buried power rail; forming a sacrificial plug at a contact surface on the buried power rail; applying a front-end-of-line module for forming devices in the semiconductor substrate; providing a Via, through layers applied by the front-end-module, which joins the sacrificial plug on the buried power rail; selectively removing the sacrificial plug thereby obtaining a cavity above the buried power rail; filling the cavity with a metal to electrically connect the devices with the buried power rail, wherein the sacrificial plug is formed such that the contact surface area is larger than an area of a cross-section of the Via parallel with the contact surface.

公开(公告)号：US20230170255A1

公开(公告)日：2023-06-01

申请号：US17833223

申请日：2022-06-06

Applicant: IMEC VZW

Inventor： Zheng Tao ,  Stefan Decoster

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/3213

CPC classification number: H01L21/76897 ,  H01L21/76883 ,  H01L23/5226 ,  H01L23/53252 ,  H01L21/76837 ,  H01L21/32139

Abstract: A method for forming an interconnection structure (10) for a semiconductor device is disclosed, wherein a first conductive layer is etched to form a set of third conductive lines (113) above a first and second conductive line (101, 108). At least one of the third conductive lines comprises a contacting portion forming a first via connection (114) to the second conductive line. The method further comprises forming spacers (115) on side walls of the set of third conductive lines, and forming, between two neighboring spacers, a via hole (116) extending to the underlying first conductive line. A second conductive layer is deposited, filling the via hole to form a second via connection (118) and forming a set of fourth conductive lines (119) extending between the spacers.

公开(公告)号：US20170141199A1

公开(公告)日：2017-05-18

申请号：US15345782

申请日：2016-11-08

Applicant: IMEC VZW

Inventor： Steven Demuynck ,  Zheng Tao ,  Boon Teik Chan ,  Liesbeth Witters ,  Marc Schaekers ,  Antony Premkumar Peter ,  Silvia Armini

IPC: H01L29/417 ,  H01L21/311 ,  H01L29/45 ,  H01L29/08 ,  H01L21/768 ,  H01L21/285 ,  H01L21/02 ,  H01L21/3105

CPC classification number: H01L29/41791 ,  H01L21/02115 ,  H01L21/02123 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/02186 ,  H01L21/0228 ,  H01L21/28518 ,  H01L21/28556 ,  H01L21/28562 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/76802 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/76886 ,  H01L21/76897 ,  H01L29/0847 ,  H01L29/45 ,  H01L29/66795 ,  H01L29/785

Abstract: A method for fabricating a semiconductor structure is provided. The method includes providing a patterned substrate comprising a semiconductor region and a dielectric region. A conformal layer of a first dielectric material is deposited directly on the patterned substrate. A layer of a sacrificial material is deposited overlying the conformal layer of the first dielectric material. The sacrificial material is patterned, whereby a part of the semiconductor region remains covered by the patterned sacrificial material. A layer of a second dielectric material is deposited on the patterned substrate, thereby completely covering the patterned sacrificial material. A recess is formed in the second dielectric material by completely removing the patterned sacrificial material. The exposed conformal layer of the first dielectric material is removed selectively to the semiconductor region.

公开(公告)号：US20160254161A1

公开(公告)日：2016-09-01

申请号：US15045923

申请日：2016-02-17

Applicant: IMEC VZW

Inventor： Boon Teik Chan ,  Zheng Tao ,  Nadia Vandenbroeck ,  Safak Sayan

IPC: H01L21/308 ,  H01L29/66

CPC classification number: H01L21/3081 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3086 ,  H01L29/66795

Abstract: A method for patterning an underlying layer is described, the method comprising providing a guiding layer on the underlying layer, the guiding layer comprising guiding structures and being substantially planar; providing a block-copolymer layer on the guiding layer; inducing phase separation of the block-copolymer layer in a regular pattern of structures of a first and a second polymer component, whereby one of the components aligns to the guiding structures, by chemo-epitaxy; thereafter, removing a first of the components of the block-copolymer layers completely, leaving a regular pattern of structures of the second component; providing a planarizing layer over the regular pattern of structures of the second component and the guiding layer; removing a portion of the planarizing layer, thereby leaving a regular pattern of structures of the planarizing layer at positions in between the structures of the second component, and exposing the structures of the second component; removing the structures of the second component, selectively with respect to the structures of the planarizing layer; and patterning the underlying layer, thereby using the structures of the planarizing layer as a mask.

Abstract translation: 描述了用于图案化下层的方法，所述方法包括在下层上提供引导层，所述引导层包括引导结构并且基本上是平面的; 在引导层上提供嵌段共聚物层; 诱导嵌段共聚物层以第一和第二聚合物组分的规则形式的结构相分离，由此其中一种组分通过化学外延对准引导结构; 此后，完全去除嵌段共聚物层中的第一组分，留下第二组分的规则的结构图案; 在所述第二部件和所述引导层的结构的规则图案上提供平坦化层; 去除所述平坦化层的一部分，从而在所述第二部件的结构之间的位置处留下所述平坦化层的规则的结构图案，并暴露所述第二部件的结构; 相对于平坦化层的结构选择性地去除第二部件的结构; 并对底层进行图案化，由此使用平坦化层的结构作为掩模。

公开(公告)号：US20160196975A1

公开(公告)日：2016-07-07

申请号：US14757671

申请日：2015-12-23

Applicant: IMEC VZW

Inventor： Zheng Tao ,  Kaidong Xu

IPC: H01L21/225 ,  H01L21/306 ,  H01L21/308

CPC classification number: H01L21/2253 ,  H01L21/225 ,  H01L21/266 ,  H01L21/306 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/3085 ,  H01L21/31144 ,  H01L21/8238 ,  H01L21/823821 ,  H01L21/845

Abstract: According to an aspect of the present inventive concept there is provided a method of providing an implanted region in a semiconductor structure including a first region and a second region, the method comprising: providing a first implantation mask covering the first region of the semiconductor structure, the first implantation mask including a first sacrificial layer, wherein the first sacrificial layer is formed as a spin-on-carbon (SOC) layer, and a second sacrificial layer, wherein the second sacrificial layer is formed as a spin-on-glass (SOG) layer; subjecting the semiconductor structure to an ion implantation process wherein an extension of the first implantation mask is such that ion implantation in the first region is counteracted and ion implantation in the second region is allowed wherein the second region is implanted; forming a third sacrificial layer covering the second region of the semiconductor structure, wherein the third sacrificial layer includes carbon; removing the second sacrificial layer at the first region by etching, wherein the third sacrificial layer protects the second region from being affected by said etching; and removing the first sacrificial layer at the first region and the third sacrificial layer at the second region by etching.

Abstract translation: 根据本发明构思的一个方面，提供了一种在包括第一区域和第二区域的半导体结构中提供注入区域的方法，所述方法包括：提供覆盖半导体结构的第一区域的第一注入掩模， 所述第一注入掩模包括第一牺牲层，其中所述第一牺牲层形成为自旋碳（SOC）层，以及第二牺牲层，其中所述第二牺牲层形成为旋涂玻璃（spin-on-glass） SOG）层; 对所述半导体结构进行离子注入工艺，其中所述第一注入掩模的延伸使得抵消所述第一区域中的离子注入并且允许在所述第二区域中的离子注入，其中所述第二区域被注入; 形成覆盖半导体结构的第二区域的第三牺牲层，其中第三牺牲层包括碳; 通过蚀刻去除第一区域处的第二牺牲层，其中第三牺牲层保护第二区域免受所述蚀刻的影响; 以及通过蚀刻在第一区域和第二区域去除第一牺牲层。