-
公开(公告)号：US10743411B1
公开(公告)日：2020-08-11
申请号：US16737288
申请日：2020-01-08
Inventor： Ho-Chieh Yu , Chen-Cheng-Lung Liao , Chun-Yu Lin , Hsiao-Ming Chang , Jing-Yao Chang , Tao-Chih Chang
Abstract: A ceramic substrate component suitable for high-power chips includes a ceramic substrate body and at least one raised metal pad. The ceramic substrate body has an upper surface and a lower surface opposite to the upper surface. The raised metal pad includes a base portion and a top layer. The base portion, which is attached to the upper surface of the ceramic substrate body, has a thickness between 10 and 300 micrometers, and a thermal expansion coefficient greater than the ceramic substrate body. The top layer is formed on the base portion and adapted to install a high-power chip thereon. The top layer extends an area less than the base portion but greater than the high-power chip, and has a thermal expansion coefficient greater than the ceramic substrate body. As such, damages due to thermal stress occurring between the base portion and the ceramic substrate body can be mitigated.
-
2.发明申请公开(公告)号：US20200245456A1
公开(公告)日：2020-07-30
申请号：US16737288
申请日：2020-01-08
Inventor： Ho-Chieh Yu , Chen-Cheng-Lung Liao , Chun-Yu Lin , Hsiao-Ming Chang , Jing-Yao Chang , Tao-Chih Chang
Abstract: A ceramic substrate component suitable for high-power chips includes a ceramic substrate body and at least one raised metal pad. The ceramic substrate body has an upper surface and a lower surface opposite to the upper surface. The raised metal pad includes a base portion and a top layer. The base portion, which is attached to the upper surface of the ceramic substrate body, has a thickness between 10 and 300 micrometers, and a thermal expansion coefficient greater than the ceramic substrate body. The top layer is formed on the base portion and adapted to install a high-power chip thereon. The top layer extends an area less than the base portion but greater than the high-power chip, and has a thermal expansion coefficient greater than the ceramic substrate body. As such, damages due to thermal stress occurring between the base portion and the ceramic substrate body can be mitigated.
-
3.发明授权公开(公告)号：US08742600B2
公开(公告)日：2014-06-03
申请号：US13736088
申请日：2013-01-08
Applicant: Industrial Technology Research Institute
Inventor： Jing-Yao Chang , Tao-Chih Chang , Tung-Han Chuang , Chun-Yen Lee
CPC classification number: H01L23/49811 , H01L21/76885 , H01L24/29 , H01L24/32 , H01L24/83 , H01L2224/29005 , H01L2224/29082 , H01L2224/29083 , H01L2224/29084 , H01L2224/29109 , H01L2224/29111 , H01L2224/29139 , H01L2224/29144 , H01L2224/29147 , H01L2224/29155 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/32503 , H01L2224/83065 , H01L2224/8309 , H01L2224/83091 , H01L2224/83097 , H01L2224/83191 , H01L2224/83192 , H01L2224/83193 , H01L2224/8381 , H01L2224/83825 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/15747 , H01L2924/00 , H01L2924/206 , H01L2924/00014
Abstract: Provided are a dual-phase intermetallic interconnection structure and a fabricating method thereof. The dual-phase intermetallic interconnection structure includes a first intermetallic compound, a second intermetallic compound, a first solder layer, and a second solder layer. The second intermetallic compound covers and surrounds the first intermetallic compound. The first intermetallic compound and the second intermetallic compound contain different high-melting point metal. The first solder layer and the second solder layer are disposed at the opposite sides of the second intermetallic compound, respectively. The first intermetallic compound is adapted to fill the micropore defects generated during the formation of the second intermetallic compound.
Abstract translation: 提供了一种双相金属间互连结构及其制造方法。 双相金属间互连结构包括第一金属间化合物，第二金属间化合物，第一焊料层和第二焊料层。 第二金属间化合物覆盖并围绕第一金属间化合物。 第一金属间化合物和第二金属间化合物含有不同的高熔点金属。 第一焊料层和第二焊料层分别设置在第二金属间化合物的相对侧。 第一金属间化合物适于填充在形成第二金属间化合物期间产生的微孔缺陷。
-
公开(公告)号：US20230197578A1
公开(公告)日：2023-06-22
申请号：US17667558
申请日：2022-02-09
Applicant: Industrial Technology Research Institute
Inventor： Tai-Jyun Yu , Sheng-Tsai Wu , Kuo-Shu Kao , Han-Lin Wu , Tai-Kuang Lee , Jing-Yao Chang
IPC: H01L23/495 , H01L23/00
CPC classification number: H01L23/49548 , H01L24/32 , H01L2224/32245 , H01L24/83 , H01L2224/83815
Abstract: A power semiconductor device, including a terminal base, is provided. The terminal base has a first end and a second end opposite to each other. The first end has a first flange expanding outward. The first flange is welded to a pad of a substrate by a solder. An included angle between an extension direction of the first flange and a length direction of the terminal base is greater than 90 degrees.
-
公开(公告)号：US20210066257A1
公开(公告)日：2021-03-04
申请号：US16735707
申请日：2020-01-07
Applicant: Industrial Technology Research Institute
Inventor： Wei-Kuo Han , Jing-Yao Chang , Tao-Chih Chang
IPC: H01L25/07 , H01L23/498
Abstract: An electronic device package structure including a substrate, a first circuit layer, a second circuit layer, an electronic device and an input/output device is provided. The first circuit layer includes a first conductive portion, a second conductive portion and a first curve portion located between the first conductive portion and the second conductive portion. At least a partial thickness of the first curve portion is greater than a thickness of the first conductive portion. The electronic device disposed on the second circuit layer is electrically connected to the second conductive portion of the first circuit layer. The input/output device disposed corresponding to the first conductive portion is electrically connected to the first conductive portion of the first circuit layer.
-
Patent Agency Ranking
公开(公告)号：US20180358307A1
公开(公告)日：2018-12-13
申请号：US16108272
申请日：2018-08-22
Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
Inventor： Jing-Yao Chang , Tao-Chih Chang , Fang-Jun Leu , Wei-Kuo Han , Kuo-Shu Kao
IPC: H01L23/00
CPC classification number: H01L23/562 , H01L24/33 , H01L24/83 , H01L2224/29139 , H01L2224/29144 , H01L2224/29147 , H01L2224/32503 , H01L2224/33505 , H01L2924/014 , H01L2924/3512
Abstract: An electronic package structure is provided. The electronic packaging structure includes a substrate, a conductive layer disposed on the substrate, an intermetallic compound disposed on the conductive layer, a stress buffering material disposed on the substrate and adjacent to the conductive layer, and an electronic device disposed on the conductive layer and the stress buffering material. The intermetallic compound is disposed between the electronic device and the conductive layer, between the electronic device and the stress buffering material, between the substrate and the stress buffering material, and between the conductive layer and the stress buffering material. A maximum thickness of the intermetallic compound disposed between the electronic device and the stress buffering material, between the substrate and the stress buffering material, and between the conductive layer and the stress buffering material is greater than the thickness of the intermetallic compound disposed between the electronic device and the conductive layer.
-
公开(公告)号：US20180233477A1
公开(公告)日：2018-08-16
申请号：US15487754
申请日：2017-04-14
Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
Inventor： Jing-Yao Chang , Tao-Chih Chang , Fang-Jun Leu , Wei-Kuo Han , Kuo-Shu Kao
IPC: H01L23/00
CPC classification number: H01L24/29 , H01L24/05 , H01L24/32 , H01L24/83 , H01L2224/29012 , H01L2224/29013 , H01L2224/29076 , H01L2224/291 , H01L2224/29139 , H01L2224/29147 , H01L2224/29155 , H01L2224/32245 , H01L2224/32503 , H01L2224/83192 , H01L2224/83204 , H01L2224/83439 , H01L2224/83444 , H01L2224/83447 , H01L2224/83455 , H01L2224/8381 , H01L2924/3512 , H01L2924/014 , H01L2924/00014 , H01L2924/00012
Abstract: An electronic package structure is provided. The electronic packaging structure includes a substrate, a conductive layer disposed on the substrate, an intermetallic compound disposed on the conductive layer, a stress buffering material and an electronic device. The stress buffering material is disposed on the substrate and adjacent to the conductive layer. The electronic device is disposed on the intermetallic compound and the stress buffering material, and the electronic device is in contact with the intermetallic compound. The stress buffering material is adjacent to the conductive layer to have the conductive layer and the stress buffering material together serving as a stress buffer, so as to enhance the effect of stress buffering, thereby preventing a wafer from cracking due to stress.
-
公开(公告)号：US20180019178A1
公开(公告)日：2018-01-18
申请号：US15647264
申请日：2017-07-12
Applicant: Industrial Technology Research Institute
Inventor： Yu-Min Lin , Kuo-Shu Kao , Jing-Yao Chang , Tao-Chih Chang
IPC: H01L23/367 , H01L23/13 , H01L23/31 , H01L23/373 , H05K3/00 , H05K3/32 , H05K1/18 , H01L23/00 , H05K1/02 , H01L25/065 , H05K1/11 , H01L21/56 , H01L25/10 , H01L23/538 , H01L23/492 , H01L21/48
CPC classification number: H01L23/367 , H01L21/4857 , H01L21/565 , H01L23/13 , H01L23/3121 , H01L23/36 , H01L23/3735 , H01L23/492 , H01L23/5385 , H01L23/5389 , H01L24/19 , H01L24/20 , H01L24/32 , H01L24/73 , H01L24/83 , H01L25/0655 , H01L25/105 , H01L2224/04105 , H01L2224/18 , H01L2224/211 , H01L2224/215 , H01L2224/24137 , H01L2224/24247 , H01L2224/32225 , H01L2224/32245 , H01L2224/73267 , H01L2224/83192 , H01L2224/838 , H01L2225/1023 , H01L2225/1094 , H01L2924/01029 , H01L2924/15153 , H01L2924/35 , H01L2924/37001 , H05K1/0203 , H05K1/0204 , H05K1/115 , H05K1/185 , H05K3/0047 , H05K3/108 , H05K3/32 , H05K3/4688 , H05K2201/066 , H05K2201/09827 , H05K2201/10416
Abstract: A chip packaging includes a substrate, a first chip, a molding material, a first circuit, and a second circuit. The substrate includes a bottom surface, a first top surface disposed above the bottom surface with a first height, and a second top surface disposed above the bottom surface with a second height. The first height is smaller than the second height. The first chip is disposed on the first top surface. The molding material is disposed on the substrate and covers the first chip. The first and second circuits are disposed on the molding material, and are respectively and electrically connected to the first chip and the second top surface of the substrate. The substrate is made of copper material with huge area and has the properties of high current withstand capacity and high thermal efficiency. The second top surface protects the first chip from damage.
-
9.发明授权公开(公告)号：US11239211B2
公开(公告)日：2022-02-01
申请号：US16735707
申请日：2020-01-07
Applicant: Industrial Technology Research Institute
Inventor： Wei-Kuo Han , Jing-Yao Chang , Tao-Chih Chang
IPC: H01L23/48 , H01L21/44 , H05K7/00 , H01R9/00 , H01L25/07 , H01L23/498 , H01L23/528 , H01L23/00
Abstract: An electronic device package structure including a substrate, a first circuit layer, a second circuit layer, an electronic device and an input/output device is provided. The first circuit layer includes a first conductive portion, a second conductive portion and a first curve portion located between the first conductive portion and the second conductive portion. At least a partial thickness of the first curve portion is greater than a thickness of the first conductive portion. The electronic device disposed on the second circuit layer is electrically connected to the second conductive portion of the first circuit layer. The input/output device disposed corresponding to the first conductive portion is electrically connected to the first conductive portion of the first circuit layer.
-
公开(公告)号：US10672677B2
公开(公告)日：2020-06-02
申请号：US15979403
申请日：2018-05-14
Inventor： Jing-Yao Chang , Tao-Chih Chang , Kuo-Shu Kao , Fang-Jun Leu , Hsin-Han Lin , Chih-Ming Tzeng , Hsiao-Ming Chang , Chih-Ming Shen
IPC: H01L23/31 , H01L23/36 , H01L23/373 , H01L23/495 , H01L23/498 , H01L23/00
Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a semiconductor chip, a guard ring, a gel layer, and a first lead frame. The guard ring is disposed on the semiconductor chip, and the gel layer is disposed on the guard ring. The first lead frame is electrically connected to the semiconductor chip, and the gel layer is located between the guard ring and the first lead frame.
-
-
-
-
-
-
-
-
-
Search Results
20
records
(took 0.017 seconds)
