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    Method and apparatus for providing fault-tolerance in parallel-processing systems
    1.
    发明申请
    Method and apparatus for providing fault-tolerance in parallel-processing systems 有权
    用于在并行处理系统中提供容错的方法和装置

    公开(公告)号：US20070220298A1

    公开(公告)日：2007-09-20

    申请号：US11385429

    申请日：2006-03-20

    申请人： Kenny Gross ,  Alan Wood

    发明人： Kenny Gross ,  Alan Wood

    IPC分类号： G06F11/00

    CPC分类号： G06F11/3409 ,  G06F11/3452 ,  G06F2201/81

    摘要： A system that provides fault tolerance in a parallel processing system. During operation, the system executes a parallel computing application in parallel across a subset of computing nodes within the parallel processing system. During this process, the system monitors telemetry signals within the parallel processing system. The system analyzes the monitored telemetry signals to determine if the probability that the parallel processing system will fail is increasing. If so, the system increases the frequency at which the parallel computing application is checkpointed, wherein a checkpoint includes the state of the parallel computing application at each computing node within the parallel processing system.

    摘要翻译： 在并行处理系统中提供容错的系统。 在操作期间，系统在并行处理系统内的计算节点的子集上并行地并行地执行并行计算应用。 在此过程中，系统监视并行处理系统内的遥测信号。 系统分析监控的遥测信号，以确定并行处理系统将失败的概率是否在增加。 如果是，则系统增加并行计算应用程序的检查点的频率，其中检查点包括并行处理系统内的每个计算节点处的并行计算应用的状态。

    Enhancing throughput and fault-tolerance in a parallel-processing system
    2.
    发明申请
    Enhancing throughput and fault-tolerance in a parallel-processing system 有权
    提高并行处理系统的吞吐量和容错能力

    公开(公告)号：US20070214394A1

    公开(公告)日：2007-09-13

    申请号：US11371998

    申请日：2006-03-08

    申请人： Kenny Gross ,  Alan Wood

    发明人： Kenny Gross ,  Alan Wood

    IPC分类号： G06F11/00

    CPC分类号： G06F11/2041 ,  G06F11/1471 ,  G06F11/2025 ,  G06F11/203 ,  G06F11/2046

    摘要： One embodiment of the present invention provides a system that enhances throughput and fault-tolerance in a parallel-processing system. During operation, the system first receives a task. Next, the system partitions N computing nodes into M set-aside nodes and N-M primary computing nodes, wherein M≧1. The system then processes the task in parallel across the N-M primary computing nodes. While doing so, the system proactively monitors the health of each of the N-M primary computing nodes. If the system detects a node in the N-M primary computing nodes to be at risk of failure, the system copies the portion of the task associated with the at-risk node to a subset of the M set-aside nodes. The system then processes the portion of the task in parallel across the subset of the M set-aside nodes while the N-M primary computing nodes continue executing.

    摘要翻译： 本发明的一个实施例提供一种提高并行处理系统中的吞吐量和容错能力的系统。 在操作过程中，系统首先接收到一个任务。 接下来，系统将N个计算节点划分为M个置换节点和N-M个主要计算节点，其中M> = 1。 然后，系统在N-M主计算节点上并行处理任务。 在这样做的同时，系统主动监控每个N-M主计算节点的运行状况。 如果系统检测到N-M主计算节点中的节点处于故障风险，则系统将与风险中节点相关联的任务的一部分复制到M个备用节点的子集。 然后，在N-M主计算节点继续执行的同时，系统跨M个备用节点的子集并行地处理任务的该部分。

    Pipe
    3.
    发明授权
    Pipe 有权

    公开(公告)号：US10107421B2

    公开(公告)日：2018-10-23

    申请号：US13983598

    申请日：2012-02-07

    申请人： Alan Wood ,  Horst Sandner

    发明人： Alan Wood ,  Horst Sandner

    IPC分类号： F16L9/12 ,  B29C71/00 ,  C08J5/00 ,  F16L11/06 ,  E21B17/01 ,  B29C47/00 ,  B29C47/90 ,  B29C71/02 ,  B29K71/00 ,  B29C47/88

    摘要： A polyetheretherketone pipe of length greater than 250 meters and a residual stress of less than 5 MPa may be made using a calibrator device (2) which includes a cone shaped opening (6) arranged to receive a molten extruded pipe shaped polymer. Attached to the front member (4) is a vacuum plate (14a) and successive vacuum plates (14b-14h) are attached to one another to define an array of vacuum plates, the vacuum plates being arranged to allow a vacuum to be applied to a pipe precursor passing through opening (16). The vacuum plates (14) also include (10) temperature control means for heating or cooling the plates and therefore heating or cooling a pipe precursor passing through the openings. With a vacuum applied to opening (6, 16) and heating/cooling the plates, an extruded hot plastics pipe is inserted into calibrator (2) via opening (6) and conveyed through opening (16) in plates (14), whereupon it is urged by the vacuum against the cylindrical surface defined by plates (14) to maintain its shape and the (15) temperature of each plate is controlled to control the rate of cooling of the pipe precursor passing through. The pipe may be cooled at a relatively slow rate so that a pipe made from a relatively fast crystallizing polymer crystallizes and the crystallinity of the pipe along its extent and throughout its thickness is substantially constant.

    UNIVERSAL WAFER CARRIER FOR WAFER LEVEL DIE BURN-IN
    6.
    发明申请
    UNIVERSAL WAFER CARRIER FOR WAFER LEVEL DIE BURN-IN 失效
    通用水平滚轮加速器

    公开(公告)号：US20070285115A1

    公开(公告)日：2007-12-13

    申请号：US11841566

    申请日：2007-08-20

    申请人： Alan Wood ,  Tim Corbett ,  Warren Farnworth

    发明人： Alan Wood ,  Tim Corbett ,  Warren Farnworth

    IPC分类号： G01R31/02 ,  G01R1/06

    CPC分类号： G01R31/2863

    摘要： A reusable burn-in/test fixture for testing unsingulated dice on a semiconductor wafer consists of two halves. The first half of the test fixture is a wafer cavity plate for receiving the wafer, and the second half establishes electrical communication between the wafer and electrical testing equipment. A rigid substrate has conductors thereon which establish electrical contact with the wafer. The test fixture need not be opened until the burn-in and electrical testing are completed. After burn-in stress and electrical testing, it is possible to establish interconnection between the single die or separate and package dice into discrete parts, arrays or clusters, either as singulated parts or as arrays.

    摘要翻译： 用于测试半导体晶片上的无引脚骰子的可重复使用的老化/测试夹具由两半组成。 测试夹具的前半部分是用于接收晶片的晶片腔板，第二半部分在晶片和电气测试设备之间建立电气连通。 刚性基板在其上具有与晶片电接触的导体。 在老化和电气测试完成之前，测试夹具不需要打开。 在老化应力和电气测试之后，可以将单个裸片或单独的封装裸片与封装裸片之间建立互为独立部件，阵列或簇的互连，或者作为单个部分或阵列。

    Methods for fabricating and filling conductive vias and conductive vias so formed
    7.
    发明申请
    Methods for fabricating and filling conductive vias and conductive vias so formed 有权
    制造和填充如此形成的导电通孔和导电通孔的方法

    公开(公告)号：US20070184654A1

    公开(公告)日：2007-08-09

    申请号：US11347153

    申请日：2006-02-03

    申请人： Salman Akram ,  William Hiatt ,  Steve Oliver ,  Alan Wood ,  Sidney Rigg ,  James Wark ,  Kyle Kirby

    发明人： Salman Akram ,  William Hiatt ,  Steve Oliver ,  Alan Wood ,  Sidney Rigg ,  James Wark ,  Kyle Kirby

    IPC分类号： H01L21/44

    CPC分类号： H01L21/76898 ,  H01L23/481 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05568 ,  H01L2224/13009 ,  H01L2224/13025 ,  H01L2224/16 ,  H01L2224/16145 ,  H01L2224/17181 ,  H01L2924/09701

    摘要： Methods for forming conductive vias include forming one or more via holes in a substrate. The via holes may be formed with a single mask, with the protective layers, bond pads, or other features of the substrate acting as hard masks in the event that a photomask is removed during etching processes. The via holes may be configured to facilitate adhesion of a dielectric coating that includes a low-K dielectric material to the surfaces thereof. A barrier layer may be formed over surfaces of each via hole. A base layer, which may comprise a seed material, may be formed to facilitate the subsequent, selective deposition of conductive material over the surfaces of the via hole. The resulting semiconductor devices, intermediate structures, and assemblies and electronic devices that include the semiconductor devices that result from these methods are also disclosed.

    摘要翻译： 用于形成导电通孔的方法包括在衬底中形成一个或多个通孔。 通孔可以用单个掩模形成，在蚀刻过程中去除光掩模的情况下，衬底的保护层，接合焊盘或其他特征用作硬掩模。 通孔可以被配置为便于将包括低K电介质材料的电介质涂层粘附到其表面上。 可以在每个通孔的表面上形成阻挡层。 可以形成可以包括种子材料的基层，以便于导电材料随后的选择性沉积在通孔的表面上。 还公开了包括由这些方法产生的半导体器件的所得半导体器件，中间结构和组件以及电子器件。